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公开(公告)号：CN105406866A
公开(公告)日：2016-03-16
申请号：CN201510917834.3
申请日：2015-12-10
Applicant: 中国航空工业集团公司西安航空计算技术研究所
IPC: H03M1/08
CPC classification number: H03M1/08 , H03M2201/644
Abstract: 本发明提供一种模数转换电路过压保护方法，包括以下步骤：1)串联限流电阻；在功能电路采样器件前端串联一个限流保护电阻，限流保护电阻阻值的选取保证(UO+UA)2/R≤RP成立；2)并联电压限幅电路；限流保护电阻后端接采样器件，并接在2只限幅电路运算放大器负端；3)正、负向限幅电路运算放大器输出端与负端二极管为硅开关二极管，反向截止电压不小于运算放大器供电电压，正向电流不小于(UO+UA)/r；本发明一种精度高且快速的电路过压保护方法，能够快速可靠地抑制电路开关噪声，有效保护采样电子元器件，对转换电路精度影响极小，保证了功能电路的可靠性，为嵌入式控制计算机系统可靠性设计提供了有力支撑。
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公开(公告)号：KR1020120021772A
公开(公告)日：2012-03-09
申请号：KR1020100079077
申请日：2010-08-17
Applicant: 서강대학교산학협력단
Inventor： 이승훈
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/002 , H03M2201/62 , H03M2201/6372 , H03M2201/644
Abstract: PURPOSE: A DAC(Digital To Analog Converter) using a two-dimensional INL(Integral Non-Linearity) bounded switching method is provided to secure linearity at an INL property by minimizing glitch energy. CONSTITUTION: A DAC(Digital To Analog Converter) uses a two-dimensional INL(Integral Non-Linearity) bounded switching method based on a current cell matrix structure. The DAC changes an input digital signal to an analog output signal. The DAC switches current cells, which form each matrix, through a column and row decoding mode. Switching through the decoding method divides a cell matrix to be equal into two from side to side as well as an up and down. The switching through the decoding method preferentially switches the cells which are located in a first quadrant and a third quadrant of the cell matrix. The cells, which are located in a second quadrant and a fourth quadrant, are secondly switched.
Abstract translation: 目的：提供使用二维INL（积分非线性）有界切换方法的DAC（数模转换器），通过最小化毛刺能量来确保INL属性的线性度。 构成：DAC（数模转换器）使用基于当前单元矩阵结构的二维INL（积分非线性）有界切换方法。 DAC将输入数字信号改变为模拟输出信号。 DAC通过列和行解码模式切换形成每个矩阵的当前单元格。 通过解码方法切换将单元矩阵从一侧到另一侧以及上下划分成两个。 通过解码方法的切换优先地切换位于单元矩阵的第一象限和第三象限中的单元。 位于第二象限和第四象限中的单元被二次切换。
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公开(公告)号：KR1020120126312A
公开(公告)日：2012-11-21
申请号：KR1020110044012
申请日：2011-05-11
Applicant: 엘지디스플레이 주식회사
Inventor： 정양석
CPC classification number: G09G3/3688 , G09G5/008 , G09G2300/0819 , G09G2310/0294 , G09G2370/08 , H03M1/0863 , H03M2201/644 , H04L7/033
Abstract: PURPOSE: A display device and a driving method thereof are provided to prevent the degradation of display quality due to glitch waveform by removing the glitch waveform flowing through a lock feedback signal wire connected between a timing controller and a source drive IC. CONSTITUTION: A clock training pattern signal in a first step is generated from a timing controller. The clock training pattern signal is transmitted to source drive ICs(S1). A CDR function of the source drive ICs is successively stabilized. The last source drive IC transmits a rock signal in high logic level to the timing controller(S2,S3). The timing controller successively transmits control data in a second step and input image video data in a third step to the source drive ICs(S4-S9). [Reference numerals] (AA,CC,EE,HH) Yes; (BB,DD,FF,GG) No; (S1) Clock training pattern transmission; (S2) CDR of Last SIC in a stability state?; (S4) Control data transmission; (S8) Input video data transmission
Abstract translation: 目的：提供一种显示装置及其驱动方法，通过去除流过连接在定时控制器和源极驱动IC之间的锁反馈信号线的毛刺波形，来防止由毛刺波形引起的显示质量的劣化。 构成：从时序控制器产生第一步中的时钟训练模式信号。 时钟训练模式信号被发送到源驱动IC（S1）。 源极驱动IC的CDR功能相继稳定。 最后的源驱动IC将高逻辑电平的摇滚信号发送到定时控制器（S2，S3）。 定时控制器在第二步骤中连续发送控制数据，并将第三步骤中的图像视频数据输入到源极驱动IC（S4-S9）。 （标号）（AA，CC，EE，HH）是; （BB，DD，FF，GG）否; （S1）时钟训练模式传输; （S2）稳定状态下的最后SIC的CDR; （S4）控制数据传输; （S8）输入视频数据传输
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公开(公告)号：KR1020110047406A
公开(公告)日：2011-05-09
申请号：KR1020090104020
申请日：2009-10-30
Applicant: 인하대학교 산학협력단
CPC classification number: H03M3/04 , H03M2201/644 , H03M2201/814 , H03M2201/932
Abstract: PURPOSE: A differential switch circuit using an NAND gate and a source amplifier is provided to reduce the over-drive voltage by reducing a swing width of a digital signal applied to a differential switch. CONSTITUTION: A current generating unit(100) is connected to a first common node(CN1) to receive uniform static current. A differential switch unit(300) is connected to the current generating unit through a first common node, and supplies uniform static current. A switch driving circuit unit(500) includes a first source amplifier(510) connected to a third NMOS transistor, a second source amplifier(530) connected to a fourth NMOS transistor, and a NAND gate connected to the first and second source amplifiers.
Abstract translation: 目的：提供使用NAND门和源极放大器的差分开关电路，通过减小施加到差分开关的数字信号的摆幅来减小过驱动电压。 构成：电流产生单元（100）连接到第一公共节点（CN1）以接收均匀的静态电流。 差动开关单元（300）通过第一公共节点连接到电流发生单元，并提供均匀的静态电流。 开关驱动电路单元（500）包括连接到第三NMOS晶体管的第一源极放大器（510），连接到第四NMOS晶体管的第二源极放大器（530）和连接到第一和第二源极放大器的与非门。
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公开(公告)号：KR1020080111644A
公开(公告)日：2008-12-24
申请号：KR1020070059849
申请日：2007-06-19
Applicant: 인하대학교 산학협력단
IPC: H03M1/08
CPC classification number: H03M1/0863 , H03M1/0827 , H03M2201/20 , H03M2201/6107 , H03M2201/644
Abstract: A switch driving circuit using source amplifier improving switching noise characteristics is provided to minimize a charge quantity stored in a parasitic capacitor of an output terminal by reducing a digital output swing width. A switch driving circuit using source amplifier improving switching noise characteristics comprises a current generator(110), a differential switch part(120), a first source amplifier(130), and a second source amplifier(140). The current generator is supplied with a predetermined current from a power supply voltage, and includes a third PMOS(P-type Metal Oxide Semiconductor) transistor(MP3) and a fourth PMOS transistor(MP4) connected in a common node(CN1) of the differential switch part. The differential switch part is connected through the current generator and the common node, is supplied with a fixed constant current, and includes a fifth PMOS transistor(MP5) and a sixth PMOS transistor(MP6) connected in the common node. The first source amplifier is connected through the fifth PMOS transistor of the differential switch part and the first node(N1). The source amplifier is connected through the sixth PMOS transistor of the differential switch part and the second Node(N2).
Abstract translation: 提供一种使用提高开关噪声特性的源极放大器的开关驱动电路，通过减少数字输出摆幅来使存储在输出端子的寄生电容器中的电荷量最小化。 使用改善开关噪声特性的源极放大器的开关驱动电路包括电流发生器（110），差分开关部分（120），第一源极放大器（130）和第二源极放大器（140）。 从电源电压向电流发生器提供预定电流，并且包括连接在所述电流发生器的公共节点（CN1）中的第三PMOS（P型金属氧化物半导体）晶体管（MP3）和第四PMOS晶体管（MP4） 差动开关部分。 差分开关部分通过电流发生器和公共节点连接，被提供固定的恒定电流，并且包括连接在公共节点中的第五个PMOS晶体管（MP5）和第六个PMOS晶体管（MP6）。 第一源极放大器通过差分开关部分的第五PMOS晶体管和第一节点（N1）连接。 源极放大器通过差分开关部分的第六个PMOS晶体管和第二个节点（N2）连接。
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Patent Agency Ranking
公开(公告)号：KR1020080042546A
公开(公告)日：2008-05-15
申请号：KR1020060111132
申请日：2006-11-10
Applicant: 엘지이노텍 주식회사
Inventor： 최희창
IPC: G09G3/296
CPC classification number: G09G3/288 , G06F1/26 , G09G2330/021 , G09G2330/04 , H03M1/0863 , H03M2201/644
Abstract: A circuit for preventing erroneous operation of an IPM is provided to prevent the IPM from being external noises by removing pulses corresponding to the external noises using a glitch filter. A circuit for preventing erroneous operation of an IPM(Intelligent Power Module) includes an IPM(100), and first and second glitch filters. The IPM receives logic signals of high and low sides and supplies the received signals to a PDP(Plasma Display Panel). The first glitch filter is formed at a front stage of a high side logic signal receiving terminal of the IPM. The second glitch filter is formed at a front stage of a low side logic signal receiving terminal of the IPM. The first and second glitch filters include a combination circuit with a resistor and a capacitor.
Abstract translation: 提供一种用于防止IPM的错误操作的电路，以通过使用毛刺滤波器去除对应于外部噪声的脉冲来防止IPM的外部噪声。 用于防止IPM（智能功率模块）错误操作的电路包括IPM（100）和第一和第二毛刺滤波器。 IPM接收高低侧的逻辑信号，并将接收到的信号提供给PDP（等离子体显示面板）。 第一毛刺滤波器形成在IPM的高侧逻辑信号接收终端的前级。 第二毛刺滤波器形成在IPM的低侧逻辑信号接收终端的前级。 第一和第二毛刺滤波器包括具有电阻器和电容器的组合电路。
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公开(公告)号：KR1020060124324A
公开(公告)日：2006-12-05
申请号：KR1020050046188
申请日：2005-05-31
Applicant: 엘지전자 주식회사
Inventor： 이승현
IPC: H03M1/76
CPC classification number: H03M1/76 , H03M3/02 , H03M2201/6107 , H03M2201/6309 , H03M2201/644 , H03M2201/718
Abstract: A differential current switch driving circuit of a digital to analog converter is provided to suppress timing skew between first and second differential signals by equalizing conversion timing of the first and second differential signals. A first differential signal generation unit(120) generates a first differential signal by inverting and delaying a digital signal received through a data input terminal by using a first inverter and a transmission gate. A second differential signal generation unit(130) generates a second differential signal by inverting and delaying the digital signal received through the data input terminal by using second and third inverters. A data latch unit(140) latches the first and second differential signals and outputs the latched signals to a differential current switch.
Abstract translation: 提供数模转换器的差分电流开关驱动电路，通过均衡第一和第二差分信号的转换定时来抑制第一和第二差分信号之间的定时偏差。 第一差分信号生成单元（120）通过使用第一反相器和传输门反相并延迟通过数据输入端子接收的数字信号来产生第一差分信号。 第二差分信号生成单元（130）通过使用第二和第三反相器反转并延迟通过数据输入端子接收的数字信号来产生第二差分信号。 数据锁存单元（140）锁存第一和第二差分信号，并将锁存的信号输出到差动电流开关。
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公开(公告)号：KR1020060098551A
公开(公告)日：2006-09-19
申请号：KR1020050017707
申请日：2005-03-03
Applicant: 엘지전자 주식회사
CPC classification number: H03M1/0863 , H03M1/742 , H03M2201/30 , H03M2201/6318 , H03M2201/644 , H03M2201/645 , H03M2201/814
Abstract: 본 발명은 커런트 스티어링 DAC의 단위 커런트 셀을 구동하기 위한 디글리치 회로에 있어서, 상기 디글리치 회로의 입력단에 구비되어, 입력단의 스위치의 온/오프에 따른 발생되는 챠지를 흡수하는 더미 스위치를 포함함을 특징으로 한다.
또한, 본 발명에서는 상기 디글리치 회로의 출력단에 버퍼부를 더 포함함을 특징으로 한다.
상기 더미 스위치는 캐패시터 또는 모스트랜지스터로 구현할 수 있다.
이상에서와 같이, 본 발명은 커런트 스티어링(Current steering) 구조의 DAC에서 커런트 셀(Current Cell)을 구동할 때, 스위치(Switch)의 온/오프(On/Off)로 발생하는 글리치 에너지(Glitch Energy)를 효과적으로 최소화하여 출력단에서 발생하는 글리치 에러(Glitch Error)를 줄여 DAC 출력의 선형성, 디퍼런셜 비 선형성(Differential Non-Linearity), 신호대잡음비(Signal-to-Noise Ratio)를 개선 시킬 수 있다.
커런트 스티어링 DAC, 디글리치, 더미 스위치-
公开(公告)号：KR1020000014640A
公开(公告)日：2000-03-15
申请号：KR1019980034148
申请日：1998-08-22
Applicant: 현대반도체 주식회사
Inventor： 김지현
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/0818 , H03M1/0863 , H03M2201/644 , H03M2201/814
Abstract: PURPOSE: The converter is to minimize glitch which is occurred at a time of code-conversion by use of input decoder having high cross point to draw rapid setting time. CONSTITUTION: The converter comprises many decoders which receive digital signal by bit unit and decode it with short delay time to output first signal and second signal that are crossed each other at high voltage level, many switch current parts which receive the first signal and the second signal respectively from the decoders and generate a first and second switching current according to the received signals, and a current mirror which receives a first and a second switching current from many switch current parts, prevents change of signal due to a feed draw phenomenon as generated by the first and second switching current and mirrors it. Thus, stable output signal is obtained by preventing change of voltage between gate and source of MOS transistor which is generated due to the feed draw phenomenon by inputting decoded signal of switch current part.
Abstract translation: 目的：转换器通过使用具有高交叉点的输入解码器来最小化在代码转换时发生的毛刺，以绘制快速设置时间。 构成：转换器包括多个解码器，它们通过位单元接收数字信号，并以较短的延迟时间对其进行解码，以输出第一个信号，并在高电压电平下交叉彼此的第二个信号，许多接收第一个信号的开关电流部分和第二个信号 信号，并且根据接收到的信号产生第一和第二开关电流，以及从许多开关电流部分接收第一和第二开关电流的电流镜，防止由于产生的馈送汲取现象引起的信号变化 通过第一和第二开关电流并对其进行镜像。 因此，通过输入开关电流部分的解码信号，防止由于馈电现象而产生的MOS晶体管的栅极和源极之间的电压变化，从而获得稳定的输出信号。
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公开(公告)号：KR1020110054128A
公开(公告)日：2011-05-25
申请号：KR1020090110659
申请日：2009-11-17
Applicant: 인하대학교 산학협력단
IPC: H03M1/66
CPC classification number: H03M1/668 , H03M1/662 , H03M2201/6128 , H03M2201/644
Abstract: PURPOSE: A digital-to-analog converter of a current-steering method using a frequency sensing circuit is provided to reduce glitch energy in an output terminal of a digital-to-analog converter by reducing a clock-feedthrough phenomenon and a charge-injection phenomenon. CONSTITUTION: A switch driving circuit unit(300) drives a digital-to-analog differential switch by using a frequency detection circuit according to the control of a frequency detection circuit(100). The frequency detection circuit transfers a control signal for driving a switch driving circuit unit according to the high speed and low speed state of the input signal. The frequency detection circuit includes a comparison unit, a detection unit, a first buffer unit, an electric charge bump circuit and a second buffer unit.
Abstract translation: 目的：提供使用频率感测电路的电流转向方法的数模转换器，以通过减少时钟馈通现象和电荷注入来减少数模转换器的输出端中的毛刺能量 现象。 构成：开关驱动电路单元（300）通过使用频率检测电路根据频率检测电路（100）的控制来驱动数模转差动开关。 频率检测电路根据输入信号的高速和低速状态传送用于驱动开关驱动电路单元的控制信号。 频率检测电路包括比较单元，检测单元，第一缓冲单元，电荷碰撞电路和第二缓冲单元。
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