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    Package for integrated devices
    11.
    发明公开
    Package for integrated devices 失效
    Gehäusefürintegrierte Schaltungen。

    公开(公告)号：EP0287870A2

    公开(公告)日：1988-10-26

    申请号：EP88105164.3

    申请日：1988-03-30

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Massironi, Angelo

    IPC: H05K3/30

    CPC classification number: H01L23/49548 ,  H01L2924/0002 ,  H05K3/308 ,  H05K3/3447 ,  H05K2201/09709 ,  H05K2201/10696 ,  H05K2201/10757 ,  H05K2201/10871 ,  H01L2924/00

    Abstract: This package for integrated devices, to be fixed on supporting plates, in particular on printed circuits, comprises contact pins (5a,5b) to be inserted in holes (2) of the supporting plates (1) and to be soldered thereto. To prevent overturning of the package, which may lead to short circuits among the components, at least some (5a) of the contact pins are provided with protruding portions (10) defining abutments cooperating with the supporting plate to limit the inclination of the package with respect to the plate.

    Abstract translation: 用于固定在支撑板上，特别是印刷电路上的集成器件的封装包括插入支撑板（1）的孔（2）中并被焊接到其上的接触销（5a，5b）。 为了防止包装翻倒，这可能导致部件之间的短路，接触销的至少一些（5a）设置有限定与支撑板配合的支座的突出部分（10），以限制包装件的倾斜度， 尊重盘子。

    Method of fabricating vertically mountable ic package
    12.
    发明专利
    Method of fabricating vertically mountable ic package 审中-公开
    制造垂直安装IC封装的方法

    公开(公告)号：JP2013065869A

    公开(公告)日：2013-04-11

    申请号：JP2012247657

    申请日：2012-11-09

    Applicant: Honeywell Internatl Inc ,  ハネウェル・インターナショナル・インコーポレーテッド

    Inventor： MCCARTHY DANIEL J ,  WITHANAWASAM LAKSHMAN S

    IPC: H01L23/12

    CPC classification number: H01L23/3121 ,  H01L21/4846 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/48247 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1064 ,  H05K3/3442 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y02P70/613

    Abstract: PROBLEM TO BE SOLVED: To provide a method of fabricating a vertically mountable integrated circuit (IC) package.SOLUTION: An integrated circuit is mounted on a printed circuit board (PCB) 36 and electrically coupled to a bond pad on the PCB 36. The bond pad is coupled with a via that is embedded in the PCB 36. The IC, the bond pad, the via, and a portion of the PCB 36 are singulated in order to create a vertically mountable IC package. The via is cut through cross-sectionally during singulation so as to expose a portion of the via and thereby provide a mountable area for the IC package. The IC package is encapsulated or housed in a dielectric material. In addition, the via is treated with a preservative or other suitable electroless metal plating deposition that prevents oxidation and promotes solderability.

    Abstract translation: 要解决的问题：提供一种制造可垂直安装的集成电路（IC）封装的方法。 解决方案：集成电路安装在印刷电路板（PCB）36上并电耦合到PCB 36上的接合焊盘。接合焊盘与嵌入在PCB 36中的通孔耦合.IC， 接合焊盘，通孔和PCB 36的一部分被切割以便形成可垂直安装的IC封装。 在分割期间通孔横截面切割，以便露出通孔的一部分，从而为IC封装提供可安装区域。 IC封装被封装或容纳在电介质材料中。 此外，通过防腐剂或其它合适的无电金属电镀沉积处理通孔，防止氧化并促进可焊性。 版权所有（C）2013，JPO＆INPIT

    Single inline package
    16.
    发明公开
    Single inline package 失效
    Gehäusemit einer Anschlussreihe。

    公开(公告)号：EP0631312A1

    公开(公告)日：1994-12-28

    申请号：EP94104613.8

    申请日：1994-03-23

    Applicant: FUJITSU LIMITED

    Inventor： Tsuji, Kazuto, c/o FUJITSU LTD ,  Kasai, Junichi, c/o FUJITSU LTD ,  Sono, Michio, c/o FUJITSU LTD ,  Taniguchi, Norio, c/o FUJITSU LTD

    IPC: H01L23/32 ,  H01L23/367

    CPC classification number: H05K3/303 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/3426 ,  H05K2201/09781 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  Y02P70/613 ,  H01L2924/00

    Abstract: A semiconductor device includes vertical placement part (12a, 12b, 12c, 12d) for mounting the semiconductor device on a surface of a circuit board (11) in a vertical position, and a connection part (14) for making electrical connections between the circuit board (11) and a semiconductor element (13). A stage (15) is provided on which the semiconductor element (13) is placed. The stage has supporting members causing the semiconductor device to vertically stand on the circuit board. Wiring boards (17, 18), stacked on a side of the stage (15) on which the semiconductor element (13) is placed, have windows (22) in which the semiconductor element (13) is located. The vertical placement part (12a, 12b, 12c, 12d) includes wiring lines extending between edges of the circuit boards facing the circuit board and peripheries of the windows. The wiring lines have ends located in the vicinity of the edges of the circuit boards and have a shape enabling the semiconductor device to be mounted on the circuit board.

    Abstract translation: 半导体器件包括用于将半导体器件在垂直位置的电路​​板（11）的表面上安装的垂直放置部分（12a，12b，12c，12d）和用于在电路板之间进行电连接的连接部分（14） 板（11）和半导体元件（13）。 设置有半导体元件（13）放置在其上的级（15）。 该台具有使半导体器件垂直放置在电路板上的支撑构件。 堆叠在其上放置半导体元件（13）的平台（15）的一侧的接线板（17,18）具有半导体元件（13）所在的窗口（22）。 垂直放置部分（12a，12b，12c，12d）包括在电路板的面向电路板的边缘和窗口的周边之间延伸的布线。 布线具有位于电路板的边缘附近的端部，并且具有能够将半导体器件安装在电路板上的形状。

    Semiconductor package
    17.
    发明公开
    Semiconductor package 失效
    Halbleiterpackung。

    公开(公告)号：EP0587294A1

    公开(公告)日：1994-03-16

    申请号：EP93306098.0

    申请日：1993-08-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Lee, Joon Ki ,  Jeong, Hyeon Jo ,  Kim, Kyung Sub ,  Kwon, Oh-sik

    IPC: H01L23/495 ,  H05K1/18

    CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/49555 ,  H01L2924/0002 ,  H05K3/303 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10568 ,  H05K2201/10696 ,  Y02P70/613 ,  H01L2924/00

    Abstract: A semiconductor package (30) comprises leads (34) which protrude from the bottom of a package body (32), and supports (36) which are formed at both ends of the package body (32) to mount the package on a printed circuit board (PCB). The supports (36) are made of the same material as the package body (32). In the package body (32), a slot (38) is formed to receive the leads (34). The supports (36) are staggered to mount the packages close to each other. Thus, there is no additional process step for forming holes in the PCB to mount the supports of the semiconductor package, and the mounting process of the package becomes simpler. The supports (36) protruding from the package body mount the package on the PCB firmly. The slot (38) receives the leads and protect the leads from being deformed by external forces, thereby improving the reliability of the semiconductor package.

    Abstract translation: 半导体封装（30）包括从封装主体（32）的底部突出的引线（34）和形成在封装主体（32）的两端的支撑件（36），以将封装安装在印刷电路 板（PCB）。 支撑件（36）由与封装主体（32）相同的材料制成。 在封装主体（32）中，形成槽（38）以接收引线（34）。 支撑件（36）交错以将包装件彼此靠近地安装。 因此，没有用于在PCB中形成孔以安装半导体封装的支撑件的附加工艺步骤，并且封装的安装过程变得更简单。 从封装体突出的支撑件（36）将封装牢固地安装在PCB上。 槽（38）接收引线并保护引线不被外力变形，从而提高半导体封装的可靠性。

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