Use of an atomic swap instruction for a shared queue
    192.
    发明公开
    Use of an atomic swap instruction for a shared queue 审中-公开
    将原子交换指令的一个瞬间队列

    公开(公告)号:EP1262870A1

    公开(公告)日:2002-12-04

    申请号:EP01304748.5

    申请日:2001-05-30

    Inventor: Jones, Andy

    CPC classification number: G06F9/546 G06F9/52

    Abstract: A processing system which comprises means for storing a plurality of items defining a queue, pointer means having a first pointer and a second pointer associated with the beginning of said queue and a second pointer associated with the back of said queue; at least one writer for adding items to said queue; at least one reader for deleting items from said queue; and means for updating said second pointer when said at least one writer adds an item to said queue, said second pointer being updated by a swap operation.

    Abstract translation: 装置,它包括用于存储物品定义队列的多个A处理系统,指针装置具有第一指针和与所述队列和与所述队列的后部相关联的第二指针的开始相关联的第二指针; 至少一个写入器,用于将项目添加到所述队列; 至少一个读取器,用于删除从所述队列项; 以及用于更新所述第二指针,当所述至少一个写入器将项目添加到队列说,所述第二指针由一个交换操作更新。

    Trigger sequencing controller
    198.
    发明授权
    Trigger sequencing controller 失效
    触发信号序列的控制装置

    公开(公告)号:EP0862115B1

    公开(公告)日:2001-12-19

    申请号:EP98300031.6

    申请日:1998-01-06

    Inventor: Warren, Robert

    CPC classification number: G06F11/3466 G06F11/348

    Abstract: There is disclosed a single chip integrated circuit device including on-chip functional circuitry and a plurality of diagnostic units connected to monitor the on-chip functional circuitry. The plurality of diagnostic units detect respective trigger conditions by comparing signals from the on-chip functional circuitry with data held in respective diagnostic registers of the diagnostic units. The single chip integrated circuit device further includes trigger sequence control circuitry arranged to receive the trigger conditions and to initiate a trigger message when a predetermined sequence of the trigger conditions is detected. There is also disclosed a method of controlling such trigger sequences.

    Computer system with debugging routine
    200.
    发明公开
    Computer system with debugging routine 审中-公开
    Rechnersystem mit Fehlersuchroutine

    公开(公告)号:EP1148422A1

    公开(公告)日:2001-10-24

    申请号:EP01300904.8

    申请日:2001-02-01

    Inventor: Phillips, Mark

    CPC classification number: G06F11/3656

    Abstract: A register of a processor is set to one value when a host is connected to the processor and to a second value when no host is connected. The processor then starts execution after reading the register contents, and in response to the second value being stored it writes a set value to a pointer storage location. When the one value is stored, it leaves the content of the pointer location unaffected.

    Abstract translation: 当主机连接到处理器时,处理器的寄存器被设置为一个值,当没有连接主机时,寄存器被设置为一个值。 然后,处理器在读取寄存器内容之后开始执行,并且响应于存储的第二值,将设置值写入指针存储位置。 当存储一个值时,它会使指针位置的内容不受影响。

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