公开(公告)号：KR1020120082771A

公开(公告)日：2012-07-24

申请号：KR1020110004261

申请日：2011-01-14

Applicant: 한국과학기술원

Inventor： 서남표 ,  김정호 ,  조동호 ,  변정건 ,  이희재 ,  최철승 ,  강덕수 ,  안승영 ,  김은정 ,  류지윤 ,  김미주 ,  차유민

IPC: H02J17/00 ,  H02J7/00 ,  H01F27/34

Abstract: PURPOSE: An automatically controlled apparatus and method for shielding a reverse current using a current sensor are provided to automatically optimize a reverse current by inducing a reverse current to flow around a wire. CONSTITUTION: A magnetic field generating device(70) generates a leakage magnetic field(711) to be shielded. A current sensor unit(721) senses a current flowing in a coil of the magnetic field generating device. The current sensor unit transmits the sensed current signal to a current size sensing unit(722) of a controller block. The current size sensing unit senses the size of the current from the transmitted current signal. A phase detection unit(723) detects the phase of the current from the current signal detected from the current sensor unit. A shield current calculation unit(724) produces proper size and phase values of the shield current from size and phase information of the current.

Abstract translation: 目的：提供一种使用电流传感器屏蔽反向电流的自动控制装置和方法，以通过引起反向电流绕电线自动优化反向电流。 构成：磁场产生装置（70）产生被屏蔽的漏磁场（711）。 电流传感器单元（721）感测在磁场产生装置的线圈中流动的电流。 当前传感器单元将感测的电流信号发送到控制器块的当前尺寸感测单元（722）。 当前尺寸感测单元从传输的电流信号中感测电流的大小。 相位检测单元（723）根据从电流传感器单元检测到的电流信号检测电流的相位。 屏蔽电流计算单元（724）根据电流的大小和相位信息产生屏蔽电流的适当尺寸和相位值。

公开(公告)号：KR101166485B1

公开(公告)日：2012-07-19

申请号：KR1020100133124

申请日：2010-12-23

Applicant: 한국과학기술원

Inventor： 김정호 ,  김희곤 ,  성하진 ,  박준서

IPC: G01R19/165

Abstract: 전류 측정 소자는 제1 도전성 패턴 및 적어도 하나의 제2 도전성 패턴을 포함한다. 제1 전도성은 패턴 기판의 제1 면에 형성된다. 적어도 하나의 제2 도전성 패턴은 제1 도전성 패턴 주변에 코일(coil) 구조의 도전 경로가 형성되도록 기판의 제2 면에 위치하는 재배선층(redistribution layer)에 형성된다. 따라서, 전류 측정 소자는 제1 도전성 패턴에 흐르는 입력 전류에 응답하여 코일 구조의 도전 경로 상에 형성되는 유도 전압에 기초하여 입력 전류의 세기를 정밀하게 측정할 수 있다.

公开(公告)号：KR1020120072407A

公开(公告)日：2012-07-04

申请号：KR1020100134135

申请日：2010-12-24

Applicant: 한국과학기술원

Inventor： 김정호 ,  김주희 ,  박준서

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: PURPOSE: A semiconductor chip, a manufacturing method thereof, and a semiconductor module including the same are provided to improve the timing margin and voltage margin of input and output signals by including a resistance structure which is electrically connected between the through silicon via and a substrate. CONSTITUTION: A through silicon via(110) passes through both sides of a substrate(170). A resistance structure(130) is electrically connected between the through silicon via and the substrate. A pad(150) is formed on the substrate with a contact or via shape. A redistribution layer(171) includes a first conductive pattern(120) and a second conductive pattern(140). The first conductive pattern electrically connects the through silicon via and the resistance structure.

Abstract translation: 目的：提供一种半导体芯片及其制造方法以及包括该半导体芯片的半导体模块，以通过包括电连接在通孔硅通孔和基板之间的电阻结构来改善输入和输出信号的时序余量和电压余量 。 构成：穿硅通孔（110）穿过衬底（170）的两侧。 电阻结构（130）电连接在贯通硅通孔和基板之间。 衬底（150）以接触或通孔形状形成在衬底上。 再分配层（171）包括第一导电图案（120）和第二导电图案（140）。 第一导电图形电连接通孔硅通孔和电阻结构。

公开(公告)号：KR101104380B1

公开(公告)日：2012-01-16

申请号：KR1020100129677

申请日：2010-12-17

Applicant: 한국과학기술원

Inventor： 김정호 ,  김기영 ,  박준서

IPC: H01L23/12 ,  H05K7/14 ,  H01L23/48

CPC classification number: H01L2224/16145

Abstract: PURPOSE: A semiconductor chip package, a semiconductor module including the same, an electronic system, and a manufacturing method of the semiconductor chip package are provided to effectively release a heat which is generated in the core region of a first semiconductor chip by arranging a plurality of second semiconductor chips in the interface region of a first semiconductor chip. CONSTITUTION: A first semiconductor chip comprises an interface region(114) which is equipped with a core region(112) and a plurality of first input-output pads(116). A plurality of second semiconductor chips(120) comprises a first side and a second side which are faced each other. The second semiconductor chip comprises a plurality of second input-output pads(122) which is electrically connected with the first input-output pad. A plurality of second semiconductor chips is arranged in the interface region in order to be directly touched with a plurality of first input-output pads. The first semiconductor chip comprises a fixing means which fixes a plurality of second semiconductor chips.

Abstract translation: 目的：提供一种半导体芯片封装，包括该半导体芯片封装的半导体模块，电子系统和半导体芯片封装的制造方法，以通过布置多个第一半导体芯片来有效地释放在第一半导体芯片的芯区域中产生的热量 的第二半导体芯片在第一半导体芯片的界面区域中。 构成：第一半导体芯片包括配备有芯区域（112）和多个第一输入 - 输出焊盘（116）的界面区域（114）。 多个第二半导体芯片（120）包括彼此面对的第一侧面和第二侧面。 第二半导体芯片包括与第一输入 - 输出焊盘电连接的多个第二输入 - 输出焊盘（122）。 多个第二半导体芯片布置在接口区域中，以便与多个第一输入 - 输出焊盘直接接触。 第一半导体芯片包括固定多个第二半导体芯片的固定装置。

公开(公告)号：KR1020100069335A

公开(公告)日：2010-06-24

申请号：KR1020080127994

申请日：2008-12-16

Applicant: 한국과학기술원

Inventor： 김정호 ,  이우진 ,  김재민

IPC: G11C11/4076 ,  G11C11/4063 ,  G11C11/407

CPC classification number: G11C11/4093 ,  G11C7/1048 ,  G11C7/1084 ,  G11C7/109 ,  G11C11/4076

Abstract: PURPOSE: A receiving terminal having an off-chip channel is provided to improve the speed of receiving a signal by receiving a parallel signal through a delay of an off-chip channel. CONSTITUTION: A plurality of off-chip transmission channels(210a,210b,210c,210n) delays one of input signal and supply a plurality of delay input signals having different delay times. A plurality of on-chip input terminals are respectively connected to a plurality of off-chip transmission channels. A plurality of on-chip input terminals are installed on the chip. A plurality of input buffers(230a,230b,230c,230n) receive a delay input signals through each on-chip input terminal and supply a plurality of internal input signals.

Abstract translation: 目的：提供具有片外信道的接收终端，以通过片外信道的延迟接收并行信号来提高接收信号的速度。 构成：多个片外传输通道（210a，210b，210c，210n）延迟输入信号之一并提供具有不同延迟时间的多个延迟输入信号。 多个片上输入端子分别连接到多个片外传输通道。 芯片上安装有多个片上输入端子。 多个输入缓冲器（230a，230b，230c，230n）通过每个片上输入端接收延迟输入信号，并提供多个内部输入信号。

公开(公告)号：KR100951552B1

公开(公告)日：2010-04-09

申请号：KR1020070137063

申请日：2007-12-26

Applicant: 한국과학기술원

Inventor： 김정호 ,  황철순 ,  박현정 ,  하명현

IPC: H01P5/18

Abstract: 듀플렉스(Duplex) 송수신 시스템이 구성되는 시스템 인 패키지의 패키지 기판에 내장되는 방향성 결합기는 외부로부터 유입되는 전자기파를 차단하고 신호선의 그라운드를 만들어 주기 위한 제1 그라운드 레이어, 상기 제1 그라운드 레이어 위에 적층되는 유전체층에 형성되는 폴디드 커플드 라인(folded coupled line) 형태의 제1 및 제2 신호라인들 및 상기 유전체층 위에 적층되어 외부로부터 유입되는 전자기파를 차단하고 신호선의 그라운드를 만들어 주기 위한 제2 그라운드 레이어를 포함한다.

公开(公告)号：KR1020090108193A

公开(公告)日：2009-10-15

申请号：KR1020080033490

申请日：2008-04-11

Applicant: 한국과학기술원

Inventor： 김정호 ,  유충현 ,  박준서

IPC: H01L23/12 ,  H01L23/52

CPC classification number: H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PURPOSE: A stacked chip package including a through wafer via is provided to stably supply a power source by transmitting signals to through wafer via or wire bond after dividing the signals according to frequencies. CONSTITUTION: A stacked chip package(700) includes a semiconductor substrate(780), a plurality of semiconductor chips(710,720,730,740), a plurality of first through wafer vias(713), and a plurality of second through wafer vias(711a,711b,712a,712b). The semiconductor chips are laminated on the semiconductor substrate. The first through wafer vias are formed on a first same coordinate of the semiconductor chips, penetrate the semiconductor chips, and transmit a high frequency signal. The second through wafer vias are formed on a second same coordinate different from the first same coordinate, penetrate the semiconductor chips, and transmit a low frequency signal.

Abstract translation: 目的：提供包括贯通晶片通孔的堆叠式芯片封装，以便根据频率对信号进行分割后，通过传输信号到晶圆通孔或引线键来稳定地供电。 构成：堆叠式芯片封装（700）包括半导体衬底（780），多个半导体芯片（710,720,730,740），多个第一到晶圆通孔（713）和多个第二通孔晶片通孔（711a，711b， 712A，712B）。 半导体芯片层叠在半导体基板上。 第一贯穿晶片通孔形成在半导体芯片的第一相同坐标上，穿透半导体芯片并传输高频信号。 第二贯穿晶片通孔形成在不同于第一相同坐标的第二相同坐标上，穿透半导体芯片，并传输低频信号。

公开(公告)号：KR1020090081580A

公开(公告)日：2009-07-29

申请号：KR1020080007526

申请日：2008-01-24

Applicant: 한국과학기술원

Inventor： 김정호 ,  박종배 ,  유정식

IPC: H01L23/12

Abstract: A semiconductor package substrate is provided to reduce a noise generated through the cutout by including a dually stacked EBG(Electromagnetic Band Gap) structure around cutouts. A semiconductor package substrate(100) includes a ground plane(120), a power plane(140), a plurality of first EBG planes(160), a plurality of second EBG planes(180). The ground plane provides the ground voltage. The power plane provides the power supply voltage. The power plane is parallel to the ground plane. A plurality of first EBG planes are positioned between the ground plane and the power plane. The plurality of first EBG planes surround a cutout(150) formed in the ground plane or the power plane. The plurality of second EBG planes are positioned between the ground plane and the power plane. The plurality of second EBG planes surround the cutout. The plurality of second EBG planes are formed with the laminating structure with the first EBG planes.

Abstract translation: 提供半导体封装基板，通过在切口周围包括双重层叠的EBG（电磁带隙）结构来减少通过切口产生的噪声。 半导体封装基板（100）包括接地平面（120），电源平面（140），多个第一EBG平面（160），多个第二EBG平面（180）。 接地层提供接地电压。 电源提供电源电压。 电源平面平行于接地平面。 多个第一EBG平面位于接地平面和电源平面之间。 多个第一EBG平面围绕形成在接地平面或电源平面中的切口（150）。 多个第二EBG平面位于接地平面和电源平面之间。 多个第二EBG平面围绕该切口。 多个第二EBG平面与具有第一EBG平面的层压结构形成。

公开(公告)号：KR1020090081571A

公开(公告)日：2009-07-29

申请号：KR1020080007513

申请日：2008-01-24

Applicant: 한국과학기술원

Inventor： 김정호 ,  유정식 ,  박종배

IPC: H01L23/538

CPC classification number: H01L23/552 ,  H01L21/76897 ,  H01L23/481 ,  H01L23/64

Abstract: A semiconductor package substrate with a double stacked electromagnetic bandgap structure is provided to reduce the voltage drop of return current in order to smoothen signal transmission and to prevent noise coupling. A semiconductor package substrate(100) comprises a ground plane(120), a power plane(140), a via hole(150), a plurality of first EBG planes(160) and a plurality of second EBG planes(180). The ground plane provides ground voltage. The power plane provides power supply voltage. The power plane is parallel to the ground plane. The via hole delivers signals through the ground plane and power plane. The first EBG planes are positioned between the ground plane and the power plane. The first EBG planes surround the via hole. The second EBG planes are positioned between the ground plane and the power plane. The second EBG planes surround the via hole. The first and second EBG planes are laminated.

Abstract translation: 提供具有双层电磁带隙结构的半导体封装基板，以减少返回电流的电压降，以平滑信号传输并防止噪声耦合。 半导体封装基板（100）包括接地平面（120），电源平面（140），通孔（150），多个第一EBG平面（160）和多个第二EBG平面（180）。 接地层提供接地电压。 电源提供电源电压。 电源平面平行于接地平面。 通孔通过接地层和电源平面传送信号。 第一EBG平面位于接地平面和电源平面之间。 第一个EBG平面围绕通孔。 第二个EBG平面位于接地平面和电源平面之间。 第二个EBG平面围绕通孔。 第一和第二EBG平面被层压。

公开(公告)号：KR1020090069411A

公开(公告)日：2009-07-01

申请号：KR1020070137063

申请日：2007-12-26

Applicant: 한국과학기술원

Inventor： 김정호 ,  황철순 ,  박현정 ,  하명현

IPC: H01P5/18

CPC classification number: H01P5/18 ,  H01P1/36 ,  H01P3/08 ,  H01P5/19

Abstract: A directional coupler and a system-in-package of a duplex transceiver including the same are provided to reduce a size of a directional coupler by designing a first signal line and a second signal line into a folded coupled line shape. A directional coupler includes a first ground layer(20), a second ground layer(40), a first signal line, and a second signal line(70). The first ground layer blocks an external electromagnetic wave. The first signal line and the second signal line are formed on a dielectric layer(30) into a folded coupled shape. The dielectric layer is laminated on the first ground layer. The second ground layer is laminated on the dielectric layer in order to block the external electromagnetic wave. The first ground layer and the second ground layer form a ground for the first signal line and the second signal line. The first signal line and the second signal line are a strip transmission line.

Abstract translation: 提供了包括该双向收发器的定向耦合器和系统级封装，以通过将第一信号线和第二信号线设计成折叠耦合的线形来减小定向耦合器的尺寸。 定向耦合器包括第一接地层（20），第二接地层（40），第一信号线和第二信号线（70）。 第一接地层阻挡外部电磁波。 第一信号线和第二信号线形成在电介质层（30）上，形成折叠形状。 介电层层叠在第一接地层上。 第二接地层被层叠在电介质层上以阻挡外部电磁波。 第一接地层和第二接地层形成第一信号线和第二信号线的接地。 第一信号线和第二信号线是带状传输线。