-
公开(公告)号：KR1020100026839A
公开(公告)日：2010-03-10
申请号：KR1020080085999
申请日：2008-09-01
Applicant: 한국전자통신연구원
IPC: G05F3/24
CPC classification number: G05F3/30
Abstract: PURPOSE: A band gap reference voltage generator is provided to supply a reference voltage under 1V regardless of temperature variation while reducing the number of resistor which requires large area. CONSTITUTION: A band gap reference voltage generator includes a third and fourth resistance(R3-R4), a first and second bipolar transistor, and fourth and fifth NMOS transistor(M4-M5). The PMOS transistor has a gate and a source which are connected to a first node and a power terminal in common and has a drain connected to 2-4 nodes respectively. A feedback amplifier has inverting and non-inverting terminal which are connected to the second and third node respectively. The first and second bipolar transistor has emitters which are connected to a fifth node and the third node and has collector and base which are connected to the ground.
Abstract translation: 目的：提供带隙参考电压发生器，以提供低于1V的参考电压，而不管温度变化如何，同时减少需要大面积的电阻器的数量。 构成：带隙基准电压发生器包括第三和第四电阻（R3-R4），第一和第二双极晶体管以及第四和第五NMOS晶体管（M4-M5）。 PMOS晶体管具有栅极和源极，其共同连接到第一节点和电源端子，并且具有分别连接到2-4个节点的漏极。 反馈放大器具有分别连接到第二和第三节点的反相和非反相端子。 第一和第二双极晶体管具有连接到第五节点和第三节点并且具有连接到地的集电极和基极的发射极。
-
公开(公告)号：KR100925034B1
公开(公告)日：2009-11-03
申请号：KR1020070057601
申请日：2007-06-13
Applicant: 한국전자통신연구원
IPC: H03K19/0175
CPC classification number: H03K19/018528 , H03K19/0948
Abstract: 본 발명은 비동기 디지털 신호레벨 변환회로에 관한 것으로, 제 1 전압레벨의 입력신호를 제 2 전압레벨의 신호로 전압레벨을 변환하는 디지털 신호레벨 변환회로에 있어서, 입력신호의 전압레벨이 변화되는 경우, 입력신호의 빠른 전압레벨 변환을 위해 제 1 전압레벨의 입력신호가 제 2 전압레벨의 신호로 변환되는 제 1, 2 노드를, 전압레벨 변환 과정동안 상기 제 2 전압레벨을 갖는 제 2 전원전압에 연결되도록 함으로써, 신호레벨 변환속도가 개선된 것을 특징으로 한다.
레벨변환, 이중전원전압, CCLC, 변환 속도-
公开(公告)号：KR100916307B1
公开(公告)日：2009-09-10
申请号：KR1020070104108
申请日：2007-10-16
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1225 , H03M1/167
Abstract: 본 발명은 제1 디지털 신호를 아날로그 신호로 변환하는 DAC(Digital Analog Converter), 상기 DAC로부터 출력되는 신호 및 제1 SHA(Sample and Hold Amplifier)로부터 입력되는 아날로그 신호의 차를 구하는 감산기, 상기 감산된 신호를 증폭하는 증폭기, 상기 제1 SHA의 출력단 및 상기 증폭기의 입력단과 제1 스위치부를 통하여 결합하는 제1 커패시터부, 상기 증폭기의 입력단 및 상기 증폭기의 출력단과 제2 스위치부를 통하여 결합하는 제2 커패시터부 및 상기 증폭기의 입력단 및 상기 증폭기의 출력단과 제3 스위치부를 통하여 결합하는 제3 커패시터부를 포함하는 MDAC(Multiplying-DAC)가 구비된 것을 특징으로 하는 알고리즈믹 아날로그 디지털 변환기를 제공할 수 있다.
알고리즈믹 아날로그 디지털 변환기, MDAC-
公开(公告)号：KR1020090035358A
公开(公告)日：2009-04-09
申请号：KR1020070100603
申请日：2007-10-05
Applicant: 한국전자통신연구원
IPC: H03G3/20
CPC classification number: H03G1/0094 , H03F3/005 , H03F3/45475
Abstract: A switched capacitor variable gain amplifier is provided to reduce a voltage gain error due to capacitor mismatching by sharing a sampling capacitor in a sampling phase and an amplifying phase. A first sampling capacitor module(320A) and a second sampling capacitor module(320B) include a first sampling capacitor and a first variable capacitor and stores an input voltage in the sampling phase respectively. An operational amplifier amplifies the difference between input voltages in the amplifying phase. A first amplifying capacitor module(330A) and a second amplifying capacitor module(330B) share the first and second sampling capacitor modules and the first sampling capacitor and determine a voltage gain value of the input voltage according to the capacitance of a compensation capacitor, a second variable capacitor, and the shared first sampling capacitor. A plurality of sampling switches(340) and amplifying switches(350) are opened or closed in the sampling phase and the amplifying phase.
Abstract translation: 提供开关电容器可变增益放大器，以通过在采样阶段和放大阶段共享采样电容器来减少由于电容器失配引起的电压增益误差。 第一采样电容器模块（320A）和第二采样电容器模块（320B）包括第一采样电容器和第一可变电容器，并且分别在采样相位中存储输入电压。 运算放大器放大放大阶段的输入电压之差。 第一放大电容器模块（330A）和第二放大电容器模块（330B）共享第一和第二采样电容器模块和第一采样电容器，并根据补偿电容器的电容确定输入电压的电压增益值， 第二可变电容器和共享的第一采样电容器。 多个采样开关（340）和放大开关（350）在采样阶段和放大阶段被打开或关闭。
-
公开(公告)号：KR1020090033980A
公开(公告)日：2009-04-07
申请号：KR1020070099082
申请日：2007-10-02
Applicant: 한국전자통신연구원
IPC: H03G3/20
CPC classification number: H03F3/45973 , H03F1/02 , H03F3/005 , H03F3/45475 , H03F2203/45136 , H03F2203/45514 , H04N5/335 , H04N5/378
Abstract: A dual CDS/PxGA(Correlated Double Sampling/Pixel Gain Amplifier) circuit is provided to obtain a wide variable gain by controlling the capacitance by the capacitor arrangement. A first sampling unit(310) samples a reset level and a data level of a first pixel. A second sampling unit(320) samples the reset level and the data level of a second pixel. An operational amplifier(330) receives a sampling value from the first sampling unit and the second sampling unit. The operational amplifier calculates the output signal of the first pixel and the output signal of the second pixel by using the sampling value and amplifies and outputs the calculated signal. The gain of the operational amplifier is decided based on the capacitance of the capacitors included in the first sampling unit and the second sampling unit.
Abstract translation: 提供双CDS / PxGA（相关双采样/像素增益放大器）电路以通过电容器布置控制电容来获得宽的可变增益。 第一采样单元（310）对第一像素的复位电平和数据电平进行采样。 第二采样单元（320）对第二像素的复位电平和数据电平进行采样。 运算放大器（330）从第一采样单元和第二采样单元接收采样值。 运算放大器通过使用采样值来计算第一像素的输出信号和第二像素的输出信号，并放大并输出计算出的信号。 运算放大器的增益基于包括在第一采样单元和第二采样单元中的电容器的电容来确定。
-
Patent Agency Ranking
公开(公告)号：KR1020090013312A
公开(公告)日：2009-02-05
申请号：KR1020070077314
申请日：2007-08-01
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1245 , H03M1/002 , H03M1/44
Abstract: A control method of pipeline analog/digital converter and a pipeline analog/digital converter are provided to minimize sampling mismatch by controlling a sampling point. A pipeline analog/digital converter does not use a shear sample-and-hold amplifier. A first stage of the pipeline analog/digital converter comprises an A/D converter and a residual signal generator. The A/D converter(420) samples the analog input signal and produces first sampling value. The A/D converter amplifies the first sampling value and converses the first sampling value to corresponding digital code. The residual signal generator(410) samples an analog input signal at the same time with the sampling by the A/D converter and produces second sampling value. While the A/D converter amplifies the first sampling value, the residual signal generator holds the second sampling value. The residual signal generator produces the residual signal by using the second sampling value and digital code and delivers the generated residual signal to the second stage.
Abstract translation: 提供管线模拟/数字转换器和流水线模拟/数字转换器的控制方法，以通过控制采样点来最小化采样失配。 管道模拟/数字转换器不使用剪切采样和保持放大器。 管线模拟/数字转换器的第一级包括A / D转换器和残余信号发生器。 A / D转换器（420）对模拟输入信号进行采样并产生第一采样值。 A / D转换器放大第一采样值并将第一采样值转换为相应的数字码。 残余信号发生器（410）通过A / D转换器的采样同时对模拟输入信号进行采样，并产生第二采样值。 当A / D转换器放大第一采样值时，剩余信号发生器保持第二采样值。 剩余信号发生器通过使用第二采样值和数字码产生残余信号，并将产生的残留信号传送到第二级。
-
公开(公告)号：KR100874700B1
公开(公告)日：2008-12-18
申请号：KR1020070057137
申请日：2007-06-12
Applicant: 한국전자통신연구원
IPC: H01L29/73
Abstract: A high-speed low-voltage differential signal driving unit using a method for fabricating a bipolar transistor is provided to embody a differential signal driving circuit capable of operating at a high speed by replacing a switching device of a differential signal driving circuit by a bipolar transistor of a field effect transistor. A differential signal driving circuit(420) switches an inputted differential signal to output a common mode voltage through a first output node and a second output node. A common mode feedback circuit(410) supplies predetermined current to the differential signal driving circuit or receives predetermined current from the differential signal driving circuit according to the common mode voltage. The differential signal driving circuit includes a common mode voltage output part for outputting a common mode voltage of the differential signal driving circuit wherein the common mode voltage output part connects the first and second output nodes. The differential signal is inputted through two bipolar transistors. The common mode voltage output part can include first and second resistors between the first and second output nodes wherein the common mode voltage is outputted through an intermediate node that connects the first and second resistors.
Abstract translation: 提供一种使用制造双极晶体管的方法的高速低压差分信号驱动单元，以通过用双极晶体管替换差分信号驱动电路的开关器件来实现能够高速工作的差分信号驱动电路 场效应晶体管。 差分信号驱动电路（420）切换输入的差分信号以通过第一输出节点和第二输出节点输出共模电压。 共模反馈电路（410）根据共模电压向差分信号驱动电路提供预定电流或从差分信号驱动电路接收预定电流。 差分信号驱动电路包括共模电压输出部分，用于输出差分信号驱动电路的共模电压，其中共模电压输出部分连接第一和第二输出节点。 差分信号通过两个双极晶体管输入。 共模电压输出部分可以包括第一和第二输出节点之间的第一和第二电阻器，其中共模电压通过连接第一和第二电阻器的中间节点输出。
-
公开(公告)号：KR1020080052236A
公开(公告)日：2008-06-11
申请号：KR1020070057137
申请日：2007-06-12
Applicant: 한국전자통신연구원
IPC: H01L29/73
Abstract: A high-speed low-voltage differential signal driving unit using a method for fabricating a bipolar transistor is provided to embody a differential signal driving circuit capable of operating at a high speed by replacing a switching device of a differential signal driving circuit by a bipolar transistor of a field effect transistor. A differential signal driving circuit(420) switches an inputted differential signal to output a common mode voltage through a first output node and a second output node. A common mode feedback circuit(410) supplies predetermined current to the differential signal driving circuit or receives predetermined current from the differential signal driving circuit according to the common mode voltage. The differential signal driving circuit includes a common mode voltage output part for outputting a common mode voltage of the differential signal driving circuit wherein the common mode voltage output part connects the first and second output nodes. The differential signal is inputted through two bipolar transistors. The common mode voltage output part can include first and second resistors between the first and second output nodes wherein the common mode voltage is outputted through an intermediate node that connects the first and second resistors.
Abstract translation: 提供一种使用制造双极晶体管的方法的高速低电压差分信号驱动单元，以实现能够通过双极晶体管代替差分信号驱动电路的开关器件而能够高速工作的差分信号驱动电路 的场效应晶体管。 差分信号驱动电路（420）通过第一输出节点和第二输出节点切换输入的差分信号以输出共模电压。 共模反馈电路（410）将预定电流提供给差分信号驱动电路，或者根据共模电压从差分信号驱动电路接收预定电流。 差分信号驱动电路包括用于输出差分信号驱动电路的共模电压的共模电压输出部分，其中共模电压输出部分连接第一和第二输出节点。 差分信号通过两个双极晶体管输入。 共模电压输出部分可以包括第一和第二输出节点之间的第一和第二电阻器，其中共模电压通过连接第一和第二电阻器的中间节点输出。
-
公开(公告)号：KR1020080024676A
公开(公告)日：2008-03-19
申请号：KR1020060089083
申请日：2006-09-14
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1225 , H03M1/168
Abstract: A multi-bit pipeline analog-to-digital converter is provided to decrease a chip size by arranging amplifiers between an SHA(Sampling and Holding Agent) and an MDAC of a first stage. A multi-bit pipeline analog-to-digital converter includes an SHA(10), an N-bit flash ADC(Analog Digital Converter)(20), an N-bit MDAC(30), and a 3-stage amplifier(AMP1). The SHA samples and holds an input analog voltage and removes a sampling error from an input voltage. The N-bit flash ADCs of first to K-th stages receive an analog signal and convert the analog signal to a digital signal. The N-bit MDACs of first to K-th stages convert a difference between an output digital signal from the N-bit flash ADC and the output signal from a previous stage into an analog signal and outputs the analog signal. The 3-stage amplifier is connected to the N-bit MDAC(Multiplying Digital to Analog Converter) output of the first stage at a first clock. At a second clock, the 3-stage amplifier is connected to an output of the SHA.
Abstract translation: 提供了一种多位流水线模数转换器，通过在SHA（采样和保持代理）与第一级的MDAC之间布置放大器来减小芯片尺寸。 多位流水线模数转换器包括SHA（10），N位闪存ADC（模拟数字转换器）（20），N位MDAC（30）和3级放大器（AMP1 ）。 SHA采样并保持输入模拟电压，并从输入电压中消除采样误差。 第一至第K级的N位闪存ADC接收模拟信号，并将模拟信号转换为数字信号。 第一至第K级的N位MDAC将来自N位闪存ADC的输出数字信号与来自前一级的输出信号之间的差转换为模拟信号，并输出模拟信号。 3级放大器在第一时钟连接到第一级的N位MDAC（乘法数模转换器）输出。 在第二个时钟，3级放大器连接到SHA的输出。
-
公开(公告)号：KR100766073B1
公开(公告)日：2007-10-11
申请号：KR1020060050320
申请日：2006-06-05
Applicant: 한국전자통신연구원
IPC: H03M3/04
Abstract: 본 발명은 시그마 델타 변조기 및 시그마 델타 변조기의 디지털-아날로그 변환기에 관한 것으로, 특히 OP 앰프를 이용한 스위치드 캐패시터 구조에 적용되어 단일 입출력시 1개 캐패시터를 제안한 스위칭 기법을 이용하여 3개 레벨을 초과하는 디지털-아날로그 변환기를 구현함으로써 디지털-아날로그 변환기의 캐패시터 부정합에 의한 비선형특성을 제거하고 캐패시터 대비 디지털-아날로그 변환기의 출력 레벨 개수의 확장을 목적으로 한다. 또한 디지털-아날로그 변환기용 캐패시터를 확장함으로써 일반 디지털-아날로그 변환기를 적용하여 캐패시터 대비 디지털-아날로그 변환기의 출력 레벨수를 확장할 수 있다.
시그마 델타 변조기, 스위치드 캐패시터 구조, DAC
-
-
-
-
-
-
-
-
-
Search Results
221
records
(took 0.025 seconds)
