公开(公告)号：US20220416047A1

公开(公告)日：2022-12-29

申请号：US17777811

申请日：2020-10-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L21/265 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, and electronic equipment including the semiconductor device. According to embodiments, a semiconductor device may include a channel portion, source/drain portions in contact with the channel portion on opposite sides of the channel portion, and a gate stack intersecting the channel portion. The channel portion includes a first part extending in a vertical direction relative to the substrate and a second part extending from the first part in a lateral direction relative to the substrate.

公开(公告)号：US11476328B2

公开(公告)日：2022-10-18

申请号：US16824810

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Xiaohong Cheng ,  Qingzhu Zhang ,  Huaxiang Yin ,  Wenwu Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84

Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

公开(公告)号：US20220320424A1

公开(公告)日：2022-10-06

申请号：US17310922

申请日：2020-12-14

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Qing LUO ,  Yaxin DING ,  Hangbing LV ,  Ming LIU

IPC: H01L45/00

Abstract: The disclosure discloses a selector and a preparation method thereof. The selector includes: a substrate 1; an alternating layer 2 provided on the substrate 1, the alternating layer 2 being alternately formed by a bottom electrode layer 21 and an insulating layer 22; the alternating layer 2 is provided with a U-shaped groove; a selective layer 3 and a dielectric layer 4 being sequentially deposited in a direction from an inner wall of the U-shaped groove to a center of the U-shaped groove; and a top electrode layer 5 is filled in a concave space defined by the dielectric layer 4. The selector and the preparation method according to one or more embodiments of the disclosure can address the technical problem of high leakage current of the selector in existing technology and provide a selector with low leakage current.

公开(公告)号：US11447876B2

公开(公告)日：2022-09-20

申请号：US16962084

申请日：2018-09-21

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Xiaogen Yin ,  Chen Li ,  Anyan Du ,  Yongkui Zhang

IPC: C23F1/16 ,  H01L21/306

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

公开(公告)号：US11424323B2

公开(公告)日：2022-08-23

申请号：US17112690

申请日：2020-12-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device with a C-shaped active area and an electronic apparatus including the same is disclosed. The semiconductor device may include a first device and a second device opposite to each other on a substrate, each of which includes: a channel portion extending vertically on the substrate; source/drain portions located at the upper and lower ends of the channel portion and along the channel portion, the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack overlapping the channel portion on an inner sidewall of C-shaped structure, the gate stack has a portion surrounded by the C-shaped structure. The openings of the C-shaped structures of the two devices are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and that of the second device close to the channel portion are substantially coplanar.

公开(公告)号：US20220244872A1

公开(公告)日：2022-08-04

申请号：US17595847

申请日：2021-04-22

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Feng ZHANG ,  Qiang HUO ,  Zhisheng CHEN ,  Qirui REN

IPC: G06F3/06 ,  G11C13/00

Abstract: The present disclosure discloses a storage method, a data processing method, a device and an apparatus based on a non-volatile memory, the method comprising: acquiring a weight value that needs to be stored in the non-volatile memory; determining a conductivity value corresponding to the weight value according to a first conversion method if the non-volatile memory is a high-resistance storage device; determining a conductivity value corresponding to the weight value according to a second conversion method which is different from the first conversion method if the non-volatile memory is a low-resistance memory device; and setting the non-volatile memory according to the conductivity value to store the weight value. The non-volatile memory and the data processing method, the device, and the apparatus provided by the present disclosure solve the problem of insufficient accuracy in weight values in existing non-volatile memories, realizing the technical effect of improving storage accuracy and data processing accuracy.

公开(公告)号：US20220231144A1

公开(公告)日：2022-07-21

申请号：US17214042

申请日：2021-03-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jun LUO ,  Tianchun YE ,  Dan ZHANG

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/40 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor structure, a method for manufacturing the semiconductor structure, and a transistor. A doped structure is provided, where the doped structure includes a dopant. A surface of the doped structure is oxidized to form the oxide film. In such case, the dopant at an interface between the oxide film and the doped structure may be redistributed, and thereby a segregated-dopant layer is formed inside or at a surface of the doped structure under the oxide film. A concentration of the dopant is higher in the segregated-dopant layer than in other regions of the doped structure. After the oxide film is removed, the doped structure with a high surface doping concentration can be obtained without an additional doping process. Therefore, after a conducting structure is formed on the segregated-dopant layer, a low contact resistance between the conducting structure and the doped structure is obtained, and a device performance is improved.

公开(公告)号：US20220190169A1

公开(公告)日：2022-06-16

申请号：US17643179

申请日：2021-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66

Abstract: A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.

公开(公告)号：US20220189853A1

公开(公告)日：2022-06-16

申请号：US17545676

申请日：2021-12-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device with a sidewall interconnection structure and a method for manufacturing the same, and an electronic apparatus including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a vertical stack including a plurality of element layers, wherein each element layer of the plurality of element layers includes a plurality of semiconductor elements and a metallization layer for the plurality of semiconductor elements; and an interconnection structure laterally adjoined the vertical stack. The interconnection structure includes: an electrical isolation layer; and a conductive structure in the electrical isolation layer, wherein at least a part of a conductive structure in the metallization layer of the each element layer is in contact with and electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.

公开(公告)号：US11294660B2

公开(公告)日：2022-04-05

申请号：US16337978

申请日：2017-04-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yuanlu Xie ,  Kun Zhang ,  Haitao Sun ,  Jing Liu ,  Jinshun Bi ,  Ming Liu

IPC: G06F8/654 ,  G06F1/3296 ,  G06F13/42 ,  G06F8/71

Abstract: An apparatus and a method for configuring or updating a programmable logic device are provided. The apparatus includes a control module and a storage module connected to the control module. The control module includes: a JTAG interface for connecting the control module to a JTAG host, and a configuration interface compatible with a to-be-configured programmable logic device. The control module is configured to: after receiving a first control instruction including configuration information via the JTAG interface, store the configuration information into the storage module; and after receiving a configuration instruction, read the configuration information to configure the to-be-configured programmable logic device. A configuration clock used in a process that the control module configures the to-be-configured programmable logic device is generated from the to-be-configured programmable logic device, the control module or an external clock source.