公开(公告)号：JP2001042501A

公开(公告)日：2001-02-16

申请号：JP20464099

申请日：1999-07-19

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN KINRYU ,  KO YOSHIN

IPC: H01L21/027 ,  G03F1/36 ,  G03F1/68 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To obtain specified fidelity and to reduce the production cost by combining a part of a binary mask curve and a part of a phase shift mask curve to produce an optical characteristic curve and forming a corrected pattern of the original pattern based on the optical characteristic curve. SOLUTION: A binary mask curve (b) showing the relation of the critical dimension (x), and a phase shift mask curve (a) showing the relation of the critical dimension (x) between a corrected pattern and the original pattern are prepared. The critical value of the critical dimension x in the original pattern is selected. Then a part of the binary mask curve (b) corresponding to the region of the critical dimension (x) the original pattern larger than the critical value, and a part of the phase shift mask curve (a) corresponding to the region of the critical dimension (x) of the original pattern smaller than the critical value are combined to produce the optical characteristic curve. The corrected pattern of the original pattern is formed on the photomask based on the optical characteristic curve.

公开(公告)号：JP2001023923A

公开(公告)日：2001-01-26

申请号：JP19410299

申请日：1999-07-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  KO KOKUTAI ,  RO KATETSU

IPC: H01L23/52 ,  H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To prevent the increase of the contact resistance of a contact pad, even when the positional discrepancy of a node contact hole occurs, by forming in a dielectric layer an opening to expose to it a source/drain region, and by extending out on the top surface of the dielectric layer the upper portion of the contact pad. SOLUTION: A shallow-trench insulation structure 320 is formed in a substrate 300, gate structures 306 are formed on the substrate 300, source/drain regions 304 are formed in the exposed portions of the substrate 300 by the gate structures 306, and a dielectric layer 308 made of silicon oxide is formed on the substrate 300 by a chemical vapor deposition method. While a contact pad 312 is formed in an opening 310 after forming in the dielectric layer 308 the opening 310 to expose to it a portion of the source/drain region 304, the contact pad 312 is so formed that its upper portion is extended out on the flat top surface of the dielectric layer 308. For example, as the material of the contact pad 312, polysilicon is used preferably.

公开(公告)号：JP2000321794A

公开(公告)日：2000-11-24

申请号：JP12896299

申请日：1999-05-10

Applicant: UNITED MICROELECTRONICS CORP

Inventor： TEI RYUICHI ,  HAKU GENKICHI ,  LEE JUNG CHUL ,  RIN IKYO

IPC: H01L21/027 ,  G03F7/42

Abstract: PROBLEM TO BE SOLVED: To make it possible to remove a photoresist material in an original position by etching a target by use of a pattern on the photoresist material on an etching machine, removing part of the photoresist by use of a plasma and removing the entire photoresist by use of a solvent. SOLUTION: The step of patterning and forming a complementary type metal oxidized film semiconductor (CMOS) photosensor 10 and the stage of removing a completely dried photoresist layer 24 are executed on the same etching so as to eliminate the need for transferring the CMOS photosensor 10 onto another etching machine. The production time for forming the CMOS photosensor 10 is thereby saved. Further, the external influences from the environment decrease. The oxygen plasma in the original position is given in order to remove the portion of the dried photoresist layer 24 during executing the pattern forming step. The solvent is thereafter used in order to effectively removing another photoresist layer 24 on the polyacrylate layer of the CMOS photosensor 10.

公开(公告)号：JP2000223654A

公开(公告)日：2000-08-11

申请号：JP2226299

申请日：1999-01-29

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SEN MEICHI ,  RIN SEITOKU

IPC: H01L25/18 ,  H01L21/60 ,  H01L25/065 ,  H01L25/07 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To reduce thickness and surface area by providing a film carrier with a plurality of conductive wires arranged on an insulation film. SOLUTION: Two chips 50, 52 of different size are contained in one package of substantially the same size as that of the larger one of the chips 50, 52 such that the chip 50 has a wider surface area than the chip 52. The chip 52 is placed on same surface as the insulation film 54 of a film carrier 58, a protrusion 66 of the chip 52 is surrounded by the insulation film 54 of the film carrier 58 and a plurality of conductive wires 56 are arranged on an insulation film. These conductive wires 56 are made thinner than a conductive wire being used in another type of carrier and the width thereof is also limited.

公开(公告)号：JP2000223650A

公开(公告)日：2000-08-11

申请号：JP2226399

申请日：1999-01-29

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SEN MEICHI ,  RIN SEITOKU

IPC: H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To obtain a thin chip scale IC package for multichip having a small surface area by arranging a plurality of chips on a film carrier while facing each other using flip-chip technology and filling the space between chips with an insulating material while exposing the other side of each chip. SOLUTION: A chip scale IC package for multichip uses a film carrier 58 in order to contain multichips 50, 52, 54, 56. Two chips 50, 56 are arranged on two faces of the film carrier 58 while facing each other using flip-chip technology. Each chip 50, 52, 54, 56 has one protrusion 72 connected with the film carrier 58. The space between the chips 50, 52, 54, 56 is filled with an insulating material 76 and the other surface is exposed. Furthermore, signal transmission route is shortened in order to transmit an external signal directly by forming a conductive wire 60 on the film carrier 58.

公开(公告)号：JP2000223649A

公开(公告)日：2000-08-11

申请号：JP2226199

申请日：1999-01-29

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SEN MEICHI ,  RIN SEITOKU

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To obtain a very small chip scale IC package only slightly larger than a chip contained therein by filling the gap between chips with an insulating material to cover the element surface of two chips while exposing the back face thereof thereby forming an insulation compound. SOLUTION: First and second chips 50, 52 have element surfaces 60, 62 facing the opposite side face of a film carrier 58 and bonding pads of two chips 50, 52 are connected electrically with a conductive wire 56 on a film carrier 58 through first and second conductive protrusions 64, 66. An insulating material fills the space between two chips 50, 52 to form an insulation compound 68. The insulation compound 68 seals only the conductive protrusions 64, 66 and the element surfaces 60, 62 of the chips 50, 52 such that the back faces 70, 72 of the first and second chips 50, 52 are exposed.

公开(公告)号：JP2000216369A

公开(公告)日：2000-08-04

申请号：JP1230499

申请日：1999-01-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： HAKU GENKICHI ,  TEI RYUICHI ,  RI SEITETSU ,  RIN IKYO

IPC: H01L21/027 ,  G01J1/00 ,  G03F7/40 ,  G03F7/42 ,  H01L27/146

Abstract: PROBLEM TO BE SOLVED: To provide a process of removing a photoresist material without leaving residues on a board in a manufacture process and moreover without causing damages to it. SOLUTION: This device is provided with a cover layer 50 to be etched off later, on a substrate in a manufacture process, and also a layer of photoresist material is made on the cover layer 50. The photoresist material is patterned, exposed, and developed. The developed photoresist layer is further exposed without using masks. Using the patterned photoresist layer as a mask, the cover layer 50 is etched off. After etching, the photoresist material is removed by a solvent.

公开(公告)号：JP2000216323A

公开(公告)日：2000-08-04

申请号：JP1231099

申请日：1999-01-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YO TOKUSEI

IPC: H01L23/50

Abstract: PROBLEM TO BE SOLVED: To prevent a die pad from floating by installing a plurality of contact pads and leads in a lead frame for loading a chip and arranging the leads around the contact pads. SOLUTION: In a lead frame 40, a plurality of leads 42 are installed around a loading area 48 and a plurality of contact pads 44 near the side edges of the loading area 48. The contact pads 44 are formed by connecting the prescribed number of extending leads 42. The leads 42 selected for forming the contact pads 44 have the same voltages. The contact pads 44 are substituted for former die pads for supporting and loading chips. Thus, the contact pads 44 formed by connecting the prescribed number of extending leads 42 can be substituted for the former die pads and the occurrence of floating can be prevented in a forming step. Then, the occurrence of a crack in wire bonding can be prevented.

公开(公告)号：JP2000216240A

公开(公告)日：2000-08-04

申请号：JP983399

申请日：1999-01-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  RO KATETSU

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To avoid occurrence of an overhang structure at the upper corner part of a contact/via opening, by forming a conformal adhesive/via layer at a contact/via opening formed in a dielectrics layer, and performing an RF sputtering process before forming a conductive layer. SOLUTION: In a dielectrics layer 204 formed on a substrate 200, an opening 206 which exposes a metal structure 202 is formed. In order to cover the opening 206, an adhesive/barrier layer 206 which is conformal to the substrate 200 is formed. Then to remove an overhang structure 208a formed at the upper corner part of the opening 206, an RF sputtering process is performed. In the RF sputtering process, the gas flowing into a reactive chamber is ionized with an RF power source and an ion 209 is accelerated in an electric field. Then a conductive layer 212 is formed. Thus, no overhang structure takes place at the upper corner part of the contact/via opening, with a void removed.

公开(公告)号：JP2000208607A

公开(公告)日：2000-07-28

申请号：JP460099

申请日：1999-01-11

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO SHOGEN ,  WU JUAN-YUAN ,  RO KATETSU

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To prevent a semiconductor device from being short-circuitted due to a microscratch. SOLUTION: This method for forming an insulating part in the shape of shallow groove on a semiconductor substrate 200 is provided with a condensation process after an insulating plug 212a is chemically/physically ground. Thus, a microscratch can be prevented from forming a deep scratch by the insulating plug 212a. Therefore, short-circuitting due to the microscratch will not occur.