公开(公告)号：EP0933644A1

公开(公告)日：1999-08-04

申请号：EP99300685.7

申请日：1999-01-29

Applicant: Stmicroelectronics, Ltd.

Inventor： Maccormack, Andrew

IPC: G01R31/3185 ,  G11C29/00

CPC classification number: G11C29/32 ,  G01R31/318536

Abstract: There is described circuitry for enabling scan testing of all connections to a device, having at least one output and a plurality of inputs greater than a number of outputs. Such a device typically includes built-in self-test capability.
An exclusive-OR (80) gate receives the plurality of inputs (64,66,68) and generates an exclusive-OR output (82). A multiplexer (18) receives the at least one data output (70) and the exclusive-OR output as respect inputs, and selectively outputs one of such as a data output (72). Such selection of the output of the multiplexer is controlled responsive to a scan test signal (32), the exclusive-OR output being output from the multiplexer in a scan test.

Abstract translation: 描述了用于对具有至少一个输出和大于多个输出的多个输入的对设备的所有连接进行扫描测试的电路。 这样的设备通常包括内置的自检能力。 异或（80）门接收多个输入（64,66,68）并产生异或输出（82）。 多路复用器（18）根据输入接收至少一个数据输出（70）和异或输出，并选择性地输出诸如数据输出（72）之一。 响应于扫描测试信号（32）控制多路复用器的输出的这种选择，异或输出在扫描测试中从多路复用器输出。

公开(公告)号：EP4152744A1

公开(公告)日：2023-03-22

申请号：EP22195417.5

申请日：2022-09-13

Applicant: STMicroelectronics Ltd ,  STMicroelectronics S.r.l.

Inventor： DOMNITS, Alex ,  ROTH, Elan ,  TERZI, Davide ,  MOLINARI, Luca ,  BOSCHI, Marco

IPC: H04N9/31

Abstract: A scanning laser projector (40) includes an optical module (10) and projection engine (41). The optical module includes a laser generator outputting a laser beam, and a movable mirror (20, 24) scanning the laser beam across an exit window defined through the housing in a scanning pattern wider than the exit window such that the laser beam is directed through the exit window in a projection pattern that is smaller than and within the scanning pattern. A first light detector (18a, 18b) is positioned about a periphery of the exit window such that as the movable mirror scans the laser beam in the scan pattern, at a point in the scan pattern where the laser beam is scanned across an interior of the housing and not through the exit window, the laser beam impinges upon the first light detector. The projection engine (41) adjusts driving of the movable mirror based upon output from the first light detector (18a, 18b).

公开(公告)号：EP4089880A1

公开(公告)日：2022-11-16

申请号：EP22172296.0

申请日：2022-05-09

Applicant: STMicroelectronics Ltd ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics razvoj polprevodnikov d.o.o.

Inventor： CORDIER, Nicolas ,  CHEN, Walk ,  BLAHA, Karel

IPC: H02J50/10 ,  H02J50/80 ,  H04B5/00 ,  H04L27/02 ,  H04L27/10

Abstract: The present disclosure relates to a device comprising a frequency demodulator and an amplitude demodulator, the device being configured to use, in a first mode, both demodulators in parallel and to activate an RFID card mode or a Qi charger mode based on results provided by said demodulators.

公开(公告)号：EP3290985B1

公开(公告)日：2019-12-11

申请号：EP17162674.0

申请日：2017-03-23

Applicant: STMicroelectronics Ltd

Inventor： SOURANI, Sason

IPC: G02B26/08 ,  G09G3/34 ,  G09G3/02 ,  H02P25/032 ,  G01D5/241

公开(公告)号：EP0901080B1

公开(公告)日：2005-06-15

申请号：EP98307033.5

申请日：1998-09-02

Applicant: STMicroelectronics Ltd.

Inventor： Jones, Andrew Michael ,  Barnes, Peter Malcolm

IPC: G06F13/16

CPC classification number: G06F12/0215 ,  G06F13/1631

公开(公告)号：EP1271783A3

公开(公告)日：2004-11-03

申请号：EP02013243.7

申请日：2002-06-17

Applicant: STMicroelectronics Ltd.

Inventor： Bal, Ankur

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17736 ,  H03K19/17744

Abstract: A structure for simplifying the programmable memory to logic interface in FPGAs is proposed. The interface is such that it isolates the general purpose routing architecture for intra-PLB (Programmable Logic Blocks) routing from the RAM address, data and control lines. The programmable logic blocks and the input-output resources of the FPGA access the embedded memory or RAM using dedicated direct interconnects. A major part of these direct interconnects surface from programmable logic blocks in vicinity of the RAM. The rest run between the input-output (IO) pads/routing and the RAM blocks. A dedicated bus-routing architecture is provided to club the memories to emulate larger RAM blocks. This bus routing is devoted to interconnection among RAM blocks and is isolated from the PLB routing resources.

公开(公告)号：EP1455472A1

公开(公告)日：2004-09-08

申请号：EP03251413.5

申请日：2003-03-07

Applicant: STMicroelectronics, Ltd.

Inventor： Morris, Matt

IPC: H04J3/06

CPC classification number: H04J3/0632 ,  H04J3/0685

Abstract: A stream processing system is described in which packets of an input stream each include individual timestamps which represent relative delays between the packets. A programmable counter generates continuously count values which are compared with the timestamps in the packet stream. An output controller determines whether or not to release packets from an output port based on the result of the comparison, preferably only releasing packets when the programmable count value equals the timestamp.

Abstract translation: 描述了流处理系统，其中输入流的分组各自包括表示分组之间的相对延迟的各个时间戳。 可编程计数器产生与分组流中的时间戳相比较的连续计数值。 输出控制器基于比较的结果来确定是否从输出端口释放分组，优选地仅当可编程计数值等于时间戳时才释放分组。

公开(公告)号：EP1233517A1

公开(公告)日：2002-08-21

申请号：EP02002800.7

申请日：2002-02-07

Applicant: STMicroelectronics Ltd.

Inventor： Bal, Ankur

IPC: H03K19/177

CPC classification number: H03K19/17776

Abstract: A system for rapid configuration of reconfigurable devices with a plurality of latches (2a). The number of clock cycles for loading the configuration data are reduced by a substantial amount and the fidelity of data loaded into the configuration latches is high. The invention also incorporates procedures for configuring multiple reconfigurable devices, which are similar to the prevalent "Daisy chain" technique. The system comprises a configuration memory (11) including a plurality of memory elements (2a); a write control shift register (1) for selecting a logically continuous set of bits in the configuration memory (11); a decoder (8) for selecting one column (3) at a time of the programmable logic device; and pass transistors (10a) for connecting the input of an own memory element (2a) storing said bit to a logic '0' or a logic '1' level.

Abstract translation: 一种用于快速配置具有多个闩锁（2a）的可重新配置的装置的系统。 用于加载配置数据的时钟周期数量减少了大量，并且加载到配置锁存器中的数据的保真度很高。 本发明还包括用于配置多个可重新配置设备的过程，其类似于普遍的“菊花链”技术。 该系统包括配置存储器（11），其包括多个存储元件（2a）; 写入控制移位寄存器（1），用于选择配置存储器（11）中逻辑上连续的位组; 用于在可编程逻辑器件的时间选择一列（3）的解码器（8）; 并将用于将存储所述位的自己的存储元件（2a）的输入连接到逻辑“0”或逻辑“1”电平的晶体管（10a）。

公开(公告)号：EP1097459A1

公开(公告)日：2001-05-09

申请号：EP00929695.5

申请日：2000-05-12

Applicant: STMicroelectronics, Ltd.

Inventor： BARNES, William, Bryan

IPC: G11C29/00

CPC classification number: G11C29/40 ,  G11C29/32

Abstract: The present invention relates to a memory having sense amplifiers and data latches, the data latches being used in a test mode to form a signature register. In a normal operation mode, the data latches are form write data latches.

公开(公告)号：EP1085411A2

公开(公告)日：2001-03-21

申请号：EP00307545.4

申请日：2000-09-01

Applicant: STMicroelectronics, Ltd.

Inventor： Schann, Richard

IPC: G06F9/445

CPC classification number: G06F8/54

Abstract: An executable program is prepared from a plurality of object code modules, each object code module including section data and associated relocations and at least one of the object code modules further including code sequences at least some of which are like to be repeatedly included in the executable program. Wherever a code sequence is to be inserted a relocation instruction specifies the location of the code sequence and the code sequence is inserted into the section data at the appropriate point.
A linker is provided for preparing a executable program from such a plurality of object code modules, the linker including a relocation module for reading relocations and being operable to identify a relocation specifying one of the above-mentioned code sequences, a section data module for holding section data into which a code sequence is to be inserted, and a program preparing means which prepares the executable program including the section data with the inserted code sequences.
Also discussed is a method for assembling such an object code module and a computer program in the form of such an object code module, the computer program being co-operable with the linker to prepare said executable program.

Abstract translation: 从多个目标代码模块准备可执行程序，每个对象代码模块包括段数据和相关联的重定位，以及目标代码模块中的至少一个进一步包括代码序列，其中至少一些要被重复地包括在可执行文件 程序。 无论何时插入代码序列，重定位指令指定代码序列的位置，并将代码序列插入到适当点的段数据中。 提供了一种用于从这样的多个目标代码模块准备可执行程序的链接器，所述链接器包括用于读取重定位并可操作以用于识别指定上述代码序列中的一个的重定位的重定位模块，用于保存的段数据模块 要插入代码序列的区段数据;以及程序准备装置，其准备包含具有插入代码序列的区段数据的可执行程序。 还讨论了以这种目标代码模块的形式组装这样的目标代码模块和计算机程序的方法，该计算机程序与链接器可以协作以准备所述可执行程序。