公开(公告)号：WO1997037301A1

公开(公告)日：1997-10-09

申请号：PCT/US1996019593

申请日：1996-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  YARD, Christopher, J.

IPC: G06F09/42

CPC classification number: G06F9/3885 ,  G06F9/4484

Abstract: A microprocessor configured to detect subroutine call instructions having a target address indicative of a DSP function is provided. The detection of such instructions may be performed, for example, in an instruction decode unit within the microprocessor. Subroutine call instructions detected in this manner are routed to a digital signal processor coupled near the microprocessor or possibly integrated into the microprocessor. The microprocessor may be configured to store an indication that the DSP is enabled. If the DSP is not enabled, then the microprocessor executes the original routines stored at the target address of the instruction. Although the routines may not be as efficient in performing the DSP function, the program employing the function may still operate properly in the absence of the DSP. In this manner, a computer system may initially operate without the DSP included. If a user later decides to upgrade the computer system with a DSP, then the microprocessor may dispatch DSP functions to the DSP. Until the upgrade occurs, the microprocessor may execute the functions.

Abstract translation: 提供了被配置为检测具有指示DSP功能的目标地址的子程序调用指令的微处理器。 可以例如在微处理器内的指令解码单元中执行这种指令的检测。 以这种方式检测的子程序调用指令被路由到耦合在微处理器附近或可能集成到微处理器中的数字信号处理器。 微处理器可以被配置为存储DSP被启用的指示。 如果DSP未启用，则微处理器执行存储在指令目标地址的原始程序。 虽然程序在执行DSP功能方面可能不那么有效，但是在没有DSP的情况下，使用该功能的程序仍然可以正常工作。 以这种方式，计算机系统可以最初在不包括DSP的情况下操作。 如果用户以后决定用DSP升级计算机系统，则微处理器可以将DSP功能调度到DSP。 在升级发生之前，微处理器可以执行这些功能。

公开(公告)号：WO1997036245A1

公开(公告)日：1997-10-02

申请号：PCT/US1997005025

申请日：1997-03-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HENDRICKSON, Alan

IPC: G06F13/42

CPC classification number: G06F13/423

Abstract: A serial communication system including a serial communication port structure for starting and stopping an internal clock. This internal clock is designed, in operation, to generate a clock output signal to be transmitted to a device external to the system in which the serial communication port is incorporated. By emitting a clock output pulse train of predetermined length, the serial communication port can effectively control the passage of time as sensed by the external device. The location of data boundaries relative to the clock phase is programmable such that the data boundaries coincide with active clock edges.

Abstract translation: 一种串行通信系统，包括用于启动和停止内部时钟的串行通信端口结构。 该内部时钟在工作时被设计为产生时钟输出信号，以将其发送到并入串行通信端口的系统外部的设备。 通过发出预定长度的时钟输出脉冲串，串行通信端口可以有效地控制外部设备感测到的时间的流逝。 相对于时钟相位的数据边界的位置是可编程的，使得数据边界与活动时钟边沿重合。

公开(公告)号：WO1997036239A1

公开(公告)日：1997-10-02

申请号：PCT/US1997005117

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LEE, Sherman ,  MACDONALD, James, R. ,  WISOR, Michael, T.

IPC: G06F12/14

CPC classification number: H04L63/062 ,  G06F11/006 ,  G06F12/1408 ,  G06F21/121 ,  G06F21/73 ,  G06F21/74 ,  G06F2207/7219 ,  G06F2211/007 ,  G06F2221/0737 ,  G06F2221/2101 ,  G06F2221/2105 ,  G06F2221/2129 ,  G06F2221/2139 ,  H04L9/0897 ,  H04L9/3236 ,  H04L63/0428 ,  H04L63/0876 ,  H04L2209/12 ,  H04L2209/34 ,  H04L2463/062

Abstract: A method and apparatus for encrypting and decrypting a microprocessor serial number. First and second encryption keys and a serial number are provided in microprocessor machine specific registers. The serial number is encrypted using the first key. The encrypted serial number is encrypted using the second key. The first encryption key may be encrypted along with the serial number using the second key. The double-encrypted serial number is then stored in memory provided for that purpose.

Abstract translation: 一种用于加密和解密微处理器序列号的方法和装置。 在微处理器机器特定的寄存器中提供第一和第二加密密钥和序列号。 使用第一个密钥对序列号进行加密。 加密的序列号使用第二个密钥进行加密。 第一加密密钥可以使用第二密钥与序列号一起被加密。 然后将双重加密的序列号存储在为此目的提供的存储器中。

公开(公告)号：WO1997035301A1

公开(公告)日：1997-09-25

申请号：PCT/US1997001049

申请日：1997-01-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BARTKOWIAK, John, G.

IPC: G10L03/00

CPC classification number: G10L25/90 ,  G10L25/93

Abstract: An improved vocoder system and method for estimating pitch in a speech waveform. The method comprises an improved correlation method for estimating the pitch parameter which more accurately disregards false correlation peaks resulting from the contribution of the First Formant to the pitch estimation method. The vocoder performs a correlation calculation on a frame of the speech waveform to estimate the pitch of the frame. According to the invention, during the correlation calculation the vocoder performs calculations to determine when a transition from unvoiced to voiced speech occurs. When such a transition is detected, the vocoder widens the correlation sample window. The present invention thus determines when a transition from unvoiced to voiced speech occurs and dynamically adjusts or widens the sample window to reduce the effect of the First Formant in the pitch estimation. Once this frame and the next have been classified as voiced, the correlation sample window can be reduced to its original value. Therefore, the present invention more accurately provides the correct pitch parameter in response to a sampled speech waveform.

Abstract translation: 用于估计语音波形中的音调的改进的声码器系统和方法。 该方法包括用于估计音调参数的改进的相关方法，其更精确地忽略由第一共振峰对音调估计方法的贡献而产生的误相关峰值。 声码器对语音波形的帧执行相关计算，以估计帧的音调。 根据本发明，在相关计算期间，声码器执行计算以确定何时发生从清音到浊音的转变。 当检测到这种转换时，声码器加宽相关采样窗口。 因此，本发明确定何时发生从清音到有声语音的转变，并且动态地调整或加宽样本窗口以减少第一共振峰在音调估计中的影响。 一旦这个帧和下一个被分类为浊音，相关样本窗口可以被减小到它的原始值。 因此，本发明更准确地提供响应于采样的语音波形的正确的音调参数。

公开(公告)号：WO1997030540A1

公开(公告)日：1997-08-21

申请号：PCT/US1997001797

申请日：1997-02-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MULLINS, Jacqueline ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

IPC: H04M01/72

CPC classification number: H04M1/733 ,  H04M1/72502

Abstract: An apparatus for digital cordless telecommunications includes a frame formatter for logical channel formatting of transmitted baseband signals and received baseband signals. The apparatus comprises a radio interface connection with the frame formatter, for delivering and receiving the transmitted baseband signal and the received baseband signal, respectively, a FIFO/codec interface connected with the frame formatter, an interrupt interface connected with the frame formatter, a control register interface connected with the frame formatter, and a microcontroller interface connected with the frame formatter.

Abstract translation: 一种用于数字无绳电信的装置包括用于逻辑信道格式化发送的基带信号和接收的基带信号的帧格式化器。 该装置包括与帧格式化器的无线电接口连接，用于分别传送和接收所发送的基带信号和接收的基带信号，与帧格式器连接的FIFO /编解码器接口，与帧格式化器连接的中断接口，控制 与帧格式器连接的寄存器接口，以及与帧格式器连接的微控制器接口。

公开(公告)号：WO1997030391A1

公开(公告)日：1997-08-21

申请号：PCT/US1996016834

申请日：1996-10-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ROBERTS, David, G.

IPC: G06F09/46

CPC classification number: G06F9/52 ,  G06F13/24

Abstract: Method and system aspects properly enable and disable a function in a peripheral device. In a system aspect, the system includes a processing system, and a control mechanism within the peripheral device and coupled to the processing system, the control mechanism controlling enabling and disabling of a function in the peripheral device. The control mechanism further includes a decoder coupled to the processing system, and a counter coupled to the decoder. In a method aspect, the method includes receiving first and second control signals at a control mechanism in the peripheral device from at least one component in the processing system, and maintaining a state of the peripheral device at a predetermined level according to a value of the control mechanism, wherein the first and second control signals alter the value of the control mechanism.

Abstract translation: 方法和系统方面正确启用和禁用外围设备中的功能。 在系统方面，系统包括处理系统和外围设备内的控制机构，并且耦合到处理系统，所述控制机构控制启用和禁用外围设备中的功能。 控制机构还包括耦合到处理系统的解码器和耦合到解码器的计数器。 在方法方面，该方法包括在处理系统中的至少一个组件的外围设备中的控制机制处接收第一和第二控制信号，并且根据所述外围设备的值将外围设备的状态保持在预定级别 控制机构，其中所述第一和第二控制信号改变所述控制机构的值。

公开(公告)号：WO1997029614A1

公开(公告)日：1997-08-14

申请号：PCT/US1997001069

申请日：1997-01-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  STEWART, Brett

IPC: H04R03/00

CPC classification number: G06F1/1616 ,  G06F1/1605 ,  G06F1/1684 ,  G06F3/16 ,  H04R1/403 ,  H04R1/406 ,  H04R3/005 ,  H04R3/12

Abstract: A sound processing apparatus includes a plurality of microphones spaced apart from each other, each microphone producing electrical signals representative of sound signals incident thereon. The sound processing apparatus also includes a signal processing unit that produces a specific direction sound signal by processing the electrical signals according to a specific sound direction. The plurality of microphones can be positioned about a periphery of a computer display, and adaptative beam forming techniques can be employed to provide a directional input sound signal for use in sound processing.

Abstract translation: 声音处理装置包括彼此间隔开的多个麦克风，每个麦克风产生代表入射在其上的声音信号的电信号。 声音处理装置还包括信号处理单元，其通过根据特定声音方向处理电信号来产生特定方向声音信号。 多个麦克风可以围绕计算机显示器的周边定位，并且可以采用自适应波束形成技术来提供用于声音处理的定向输入声音信号。

公开(公告)号：WO1997029577A1

公开(公告)日：1997-08-14

申请号：PCT/US1996017585

申请日：1996-11-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KALKUNTE, Mohan

IPC: H04L29/06

CPC classification number: H04L49/9063 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031

Abstract: A network interface transmits data packets between a host computer and a network and includes a first in first out (FIFO) buffer memory with an adaptive transmit start point determined for each data packet. The network interface receives data packets from the host computer via a peripheral component interconnect (PCI) bus. A FIFO control determines the byte length of each data packet based on the header information contained in the first few received bytes of the packet. The FIFO control also measures a minimum fill time indicating the time necessary to fill the FIFO buffer memory with a predetermined minimum amount of data necessary before transmission by the FIFO buffer memory. The FIFO control calculates the time to fill the FIFO buffer memory with each packet based on the determined length and the measured minimum fill time. The time to empty the packet from the FIFO buffer memory is also calculated based upon the length of the packet and predetermined network transmission rates. If the time to empty the packet from the FIFO buffer memory is greater than or equal to the time to fill the FIFO buffer memory, the transmit start point is set to the predetermined minimum amount; otherwise, the transmit start point is adjusted in accordance with the difference in time between filling and emptying the FIFO buffer memory with the packet, a FIFO fill rate based on the measured minimum fill time, and a coefficient that accounts for latencies in the PCI bus. The network interface thus provides an optimal transmit start point for each data packet, minimizing latency and underflow conditions during network transmission.

Abstract translation: 网络接口在主计算机和网络之间传输数据分组，并包括一个先进先出（FIFO）缓冲存储器，其具有为每个数据分组确定的自适应发送起始点。 网络接口通过外围组件互连（PCI）总线从主机接收数据包。 FIFO控制基于包含在分组的前几个接收字节中的报头信息来确定每个数据分组的字节长度。 FIFO控制还测量最小填充时间，指示在FIFO缓冲存储器发送之前必须具有预定的最小数据量来填充FIFO缓冲存储器所需的时间。 FIFO控制根据确定的长度和测量的最小填充时间，计算每个数据包填充FIFO缓冲存储器的时间。 也可以基于分组的长度和预定的网络传输速率来计​​算从FIFO缓冲存储器中清空分组的时间。 如果从FIFO缓冲存储器中清空分组的时间大于或等于填充FIFO缓冲存储器的时间，则将发送开始点设置为预定的最小量; 否则，根据FIFO缓冲存储器与数据包的填充和清空之间的时间差，基于测量的最小填充时间的FIFO填充率以及考虑PCI总线中的延迟的系数来调整发送开始点 。 因此，网络接口为每个数据分组提供了最佳的发送开始点，从而最大限度地减少网络传输期间的等待时间和下溢条件。

公开(公告)号：WO1997029547A1

公开(公告)日：1997-08-14

申请号：PCT/US1996017157

申请日：1996-10-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHENG, Yi ,  RUNALDUE, Thomas, J.

IPC: H03M01/66

CPC classification number: H03M1/662 ,  H03M1/745 ,  H03M1/747

Abstract: A digital to analog converter that includes circuitry that converts sequences of positive and negative digital data samples into electrical currents and current mirror circuitry that generates an analog waveform by combining and amplifying the electrical currents.

Abstract translation: 数模转换器包括将正和负数字数据样本的序列转换为电流的电路和电流镜电路，其通过组合和放大电流来产生模拟波形。

公开(公告)号：WO1997027633A1

公开(公告)日：1997-07-31

申请号：PCT/US1996017412

申请日：1996-11-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHEN, Jian

IPC: H01L29/861

CPC classification number: H01L29/861 ,  G11C16/02 ,  G11C16/0416 ,  H01L27/115 ,  H01L29/8616

Abstract: A floating gate diode which can be used as a sourceless memory cell, and which may be arranged into an array of memory cells is disclosed. The floating gate diode comprises: a drain region (64) formed in a substrate (62); an oxide overlying and associated with the drain region (64); and a floating gate (66) overlying the oxide. Upon application of a voltage to the drain (64), a current between the drain (64) and substrate (62) is induced in proportion to an amount of electrons stored on the gate. The cells may be arranged into an array which comprises a substrate having a surface; a plurality of drain regions, one of said drain regions respectively corresponding to one of the plurality of cells, formed in the substrate; an oxide region overlying the plurality of drain regions on the surface of the substrate; and a plurality of floating gates overlying the oxide and respectively associated with the plurality of drain regions.

Abstract translation: 公开了可以用作无源存储器单元并且可以被布置成存储器单元阵列的浮置栅极二极管。 浮栅二极管包括：形成在衬底（62）中的漏区（64）; 覆盖并与漏区（64）相连的氧化物; 和覆盖氧化物的浮动栅极（66）。 在向漏极（64）施加电压时，与存储在栅极上的电子量成比例地引起漏极（64）和衬底（62）之间的电流。 电池可以被布置成包括具有表面的衬底的阵列; 多个漏极区，分别对应于所述多个单元中的一个的所述漏极区中的一个，形成在所述衬底中; 覆盖所述基板的表面上的所述多个漏极区域的氧化物区域; 以及覆盖所述氧化物并且分别与所述多个漏极区域相关联的多个浮动栅极。