公开(公告)号：JP4735867B2

公开(公告)日：2011-07-27

申请号：JP2008268529

申请日：2008-10-17

Applicant: 日本電気株式会社

Inventor： 伸一 上原 ,  研 住吉 ,  祐子 佐藤 ,  仁 松嶋 ,  節夫 金子

IPC: B29C33/38 ,  B29C33/42 ,  B29L11/00 ,  B81C1/00 ,  C03C15/00 ,  G02B3/00 ,  G02F1/1335 ,  G02F1/1337

CPC classification number: G02B3/0056 ,  B81B2207/056 ,  B81C1/00031 ,  B81C2201/0133 ,  B81C2201/0142 ,  C03C15/00 ,  C03C17/34 ,  C03C2204/08 ,  C03C2218/34 ,  G02B3/0012 ,  G02F1/133526 ,  Y10T428/131 ,  Y10T428/249969 ,  Y10T428/315

公开(公告)号：JP2009037257A

公开(公告)日：2009-02-19

申请号：JP2008268528

申请日：2008-10-17

Applicant: Nec Corp ,  日本電気株式会社

Inventor： MATSUSHIMA HITOSHI ,  UEHARA SHINICHI ,  SATO YUKO ,  SUMIYOSHI KEN ,  KANEKO SETSUO

IPC: G02B3/00 ,  B81C1/00 ,  C03C15/00 ,  G02F1/13 ,  G02F1/1335 ,  G03B21/00 ,  G03B21/14

CPC classification number: G02B3/0056 ,  B81B2207/056 ,  B81C1/00031 ,  B81C2201/0133 ,  B81C2201/0142 ,  C03C15/00 ,  C03C17/34 ,  C03C2204/08 ,  C03C2218/34 ,  G02B3/0012 ,  G02F1/133526 ,  Y10T428/131 ,  Y10T428/249969 ,  Y10T428/315

Abstract: PROBLEM TO BE SOLVED: To provide a fine structure formation method, using isotropic etching, by which controllability of etching in fine processing is improved, and even a large-sized substrate can be uniformly processed as a result. SOLUTION: The fine structure formation method is provided in which a body to be etched on the surface of which a mask having prescribed openings is disposed, is etched through the openings by using etching liquid and thereby recesses is formed on the surface of the body to be etched, wherein insoluble matter is generated by the reaction of the material contained in the body to be etched with the etching liquid, and then etching is stopped by the insoluble matter accumulated on the exposed surface of the body to be etched. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供精细的结构形成方法，使用各向同性蚀刻，通过其提高精细加工中的蚀刻的可控性，并且甚至可以均匀地加工大尺寸的基板。 解决方案：提供了一种精细的结构形成方法，其中通过使用蚀刻液蚀刻通过开口蚀刻在具有规定开口的掩模的表面上被蚀刻的物体，从而在其表面上形成凹坑 要蚀刻的物体，其中通过被蚀刻体中包含的材料与蚀刻液的反应产生不溶性物质，然后通过积体在被蚀刻体的暴露表面上的不溶性物质停止蚀刻。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006253604A

公开(公告)日：2006-09-21

申请号：JP2005071692

申请日：2005-03-14

Applicant: Omron Corp ,  オムロン株式会社

Inventor： SANO KOJI ,  MASAI MIGAKU

IPC: H01L23/02

CPC classification number: H05K7/06 ,  B81B2207/097 ,  B81C1/00301 ,  B81C1/00571 ,  B81C2201/0133 ,  B81C2201/0142 ,  B81C2203/0109 ,  B81C2203/036 ,  H01L2924/16235 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49156

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board in which a space above a surface region including at least a portion of a wiring line can securely be sealed. SOLUTION: The method includes a first step of forming a metal thin film for wiring lines on a glass substrate 11a, a second step of forming a resist pattern on the metal thin film by using a photomask 20 where a pattern for the wiring lines is formed, and a third step of forming the wiring lines by selectively removing the metal thin film by wet etching using the resist pattern as a mask. When points of the wiring lines joined with frit glass 13 are regarded as joined places, sides (La, Lb, Lc, and Ld) of the pattern for the wiring lines of the photomask 20 are bent in areas corresponding to the joined places. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造布线板的方法，其中包括至少一部分布线的表面区域之上的空间可以被牢固地密封。 解决方案：该方法包括在玻璃基板11a上形成用于布线的金属薄膜的第一步骤，通过使用其中布线图案的光掩模20在金属薄膜上形成抗蚀剂图案的第二步骤 形成线;以及第三步骤，通过使用抗蚀剂图案作为掩模通过湿蚀刻选择性地去除金属薄膜来形成布线。 将与熔结玻璃13接合的配线的点作为接合处，将光掩模20的配线的图案的侧面（La，Lb，Lc，Ld）弯曲成与接合部对应的区域。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004524172A

公开(公告)日：2004-08-12

申请号：JP2002562213

申请日：2002-02-05

Applicant: ベクトン・ディキンソン・アンド・カンパニーBecton, Dickinson And Company

Inventor： ケラー クリス ,  ディー．エヴァンス ジョン

IPC: A61B5/15 ,  A61M5/32 ,  A61M35/00 ,  A61M37/00 ,  B61C1/00 ,  B81B1/00 ,  B81C1/00

CPC classification number: A61M37/0015 ,  A61B5/14514 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150984 ,  A61M2037/003 ,  A61M2037/0053 ,  B81B2201/055 ,  B81C1/00111 ,  B81C2201/0133

Abstract: 複数の連続したプラズマ並びにウェット等方性および異方性エッチングのステップによって、マイクロ突起物アレイを、シリコンウェーハから形成する。 得られるマイクロ突起物（１４）は、ウェット等方性エッチングによって形成された鋭利な先端（１８）またはカッティングされた端を有し、各マイクロ突起物は、凹面を有する各側面（１６）を備えた実質的に角錐の形状を有する。 各マイクロ突起物の先端は、ベース（１２）と平行に延びる実質的に平坦な上面（２０）を有する。

公开(公告)号：JP2004521753A

公开(公告)日：2004-07-22

申请号：JP2002557865

申请日：2002-01-11

Applicant: インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： デポン、ミッシェル ,  ドレクスラー、ウテ ,  マグナソン、ロイ、エイチ

IPC: B81B3/00 ,  B81C1/00 ,  C23F13/14 ,  H01L21/306

CPC classification number: H01L21/30604 ,  B81B2201/12 ,  B81B2203/0118 ,  B81C1/00801 ,  B81C2201/0107 ,  B81C2201/0114 ,  B81C2201/0133 ,  C23F13/14

Abstract: 【課題】シリコン微小機械構造を望ましくない電気化学的エッチングから保護し、現況技術の欠点を克服する方法を提供すること。
【解決手段】材料および貴金属層（８）を備える微小構造の前記材料を、製造中の望ましくない電気化学的エッチングから保護する方法であって、前記構造上に前記材料よりも低い酸化還元電位を有する犠牲金属層（１２）を形成することを含み、前記犠牲金属層（１２）が前記貴金属層（８）に電気的に接続される方法。
【選択図】図４

公开(公告)号：US12024422B2

公开(公告)日：2024-07-02

申请号：US17161367

申请日：2021-01-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Enri Duqi ,  Lorenzo Baldo ,  Domenico Giusti

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/0051 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81C2201/0133 ,  B81C2203/032 ,  B81C2203/035 ,  B81C2203/0792

Abstract: An integrated device includes: a first die; a second die coupled in a stacked way on the first die along a vertical axis; a coupling region arranged between facing surfaces of the first die and of the second die, which face one another along the vertical axis and lie in a horizontal plane orthogonal to the vertical axis, for mechanical coupling of the first and second dies; electrical-contact elements carried by the facing surfaces of the first and second dies, aligned in pairs along the vertical axis; and conductive regions arranged between the pairs of electrical-contact elements carried by the facing surfaces of the first and second dies, for their electrical coupling. Supporting elements are arranged at the facing surface of at least one of the first and second dies and elastically support respective electrical-contact elements.

公开(公告)号：US11952268B2

公开(公告)日：2024-04-09

申请号：US17304094

申请日：2021-06-14

Applicant: Lawrence Semiconductor Research Laboratory, Inc.

Inventor： Chantal Arena ,  Nupur Bhargava ,  Alec Fischer

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00476 ,  B81B3/0072 ,  B81B2203/0118 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0177

Abstract: A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

公开(公告)号：US11946822B2

公开(公告)日：2024-04-02

申请号：US17290140

申请日：2019-10-16

Applicant: Sciosense B.V.

Inventor： Alessandro Faes ,  Jörg Siegert ,  Willem Frederik Adrianus Besling ,  Remco Henricus Wilhelmus Pijnenburg

IPC: G01L9/00 ,  B81B3/00 ,  B81C1/00

CPC classification number: G01L9/0073 ,  B81B3/0021 ,  B81C1/00595 ,  G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/015 ,  B81C2201/0109 ,  B81C2201/0133 ,  B81C2201/014

Abstract: In an embodiment a semiconductor transducer device includes a semiconductor body and a diaphragm having a first layer and a second layer, wherein a main extension plane of the diaphragm is arranged parallel to a surface of the semiconductor body, wherein the diaphragm is suspended at a distance from the semiconductor body in a direction perpendicular to the main extension plane of the diaphragm, wherein the second layer comprises titanium and/or titanium nitride, wherein the first layer comprises a material that is resistant to an etchant comprising fluorine or a fluorine compound, and wherein the second layer is arranged between the semiconductor body and the first layer.

公开(公告)号：US11939216B2

公开(公告)日：2024-03-26

申请号：US17188082

申请日：2021-03-01

Applicant: Infineon Technologies AG

Inventor： Andre Brockmeier ,  Stephan Helbig ,  Adolf Koller

IPC: B81C1/00 ,  G02B26/08 ,  G02B26/10

CPC classification number: B81C1/00904 ,  B81C1/00888 ,  G02B26/0833 ,  G02B26/105 ,  B81B2201/042 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0143

Abstract: A method includes producing a semiconductor wafer. The semiconductor wafer includes a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer, a first semiconductor material layer arranged at the first main surface, and a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer. The method further includes removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips. The method further includes applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.

公开(公告)号：US20230399754A1

公开(公告)日：2023-12-14

申请号：US18207569

申请日：2023-06-08

Applicant: ENTEGRIS, INC.

Inventor： Daniela White ,  Michael L. White ,  YoungMin Kim ,  Akshay Rajopadhye ,  Atanu K. Das

IPC: C23G1/18 ,  B81C1/00

CPC classification number: C23G1/18 ,  B81C1/00857 ,  B81C2201/0142 ,  B81C2201/0133

Abstract: The present disclosure relates to removal compositions for at least partially removing post-chemical mechanical polishing (post-CMP) residues from the surface of a microelectronic device. The removal compositions comprise an aqueous base composition and various molybdenum etching inhibitors that reduce the amount of molybdenum removed from the surface of the microelectronic device compared to the aqueous base composition.