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    Indexing of electronic devices using markers with different weightings
    221.
    发明授权
    Indexing of electronic devices using markers with different weightings 有权

    公开(公告)号：EP2309539B1

    公开(公告)日：2018-12-05

    申请号：EP10186952.7

    申请日：2010-10-08

    Applicant: STMicroelectronics Srl

    Inventor： Brenna, Emanuele ,  Di Franco, Antonio

    IPC: H01L23/544

    CPC classification number: H01L23/544 ,  H01L21/82 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A solution for indexing electronic devices is proposed. A corresponding electronic device (300) includes a die (320) integrating an electronic circuit (310), the die (320) having at least one index (325Rd,325Cd) including a reference (330Rd;330Cd) defining an ordered alignment of a plurality of locations (245R,250R;245C,250C) on the die (320) and marker means for defining a value of the index according to an arrangement of the marker means with respect to the reference (330Rd,330Cd); in the solution according to an embodiment of the invention, the marker means includes a plurality of markers (360Rdu,360Rdt;360Cdu,360Cdt) each one arranged at a selected one of the locations, the selected location of the marker defining a value of a digit associated with a corresponding power of a base higher than 2 within a number in a positional notation in said base representing the value of the index.

    Radiation hardened bipolar junction transistor
    222.
    发明授权
    Radiation hardened bipolar junction transistor 有权
    辐射硬化双极结型晶体管

    公开(公告)号：EP2472572B1

    公开(公告)日：2017-12-20

    申请号：EP11196036.5

    申请日：2011-12-29

    Applicant: STMicroelectronics Srl ,  STMicroelectronics Asia Pacific Pte Ltd.

    Inventor： Patti, Alfonso ,  Schillaci, Antonino ,  Marrone, Bartolomeo ,  Grasso, Gianleonardo ,  Kumar, Rajesh

    IPC: H01L21/331 ,  H01L29/732 ,  H01L29/40

    CPC classification number: H01L29/402 ,  H01L29/66272 ,  H01L29/7322

    Abstract: A method is proposed for integrating a bipolar injunction transistor (100) in a die of semiconductor material having a main surface (105) covered by a sacrificial insulating layer (110), the die including a collector region (Rc) of a first type of conductivity extending from the main surface. The method includes the steps of forming an intrinsic base region (Rbi) of a second type of conductivity extending in the collector region from the main surface through an intrinsic base window (Wbi) of the sacrificial insulating layer, and forming an emitter region (Re) of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window (We) of the sacrificial insulating layer; in the solution according to an embodiment of the invention, the method further includes the steps of removing the sacrificial insulating layer, forming an intermediate insulating layer (115) on the main surface, the intermediate insulating layer having a thickness lower than a thickness of the sacrificial layer, and forming an extrinsic base region (Rbe) of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window (Wbe) of the intermediate insulating layer, the extrinsic base region having a concentration of impurities higher than a concentration of impurities of the intrinsic base region and being separated from the emitter region by a portion of the intrinsic base region.

    A method and a structure for enhancing electrical insulation and dynamic performance of MIS structures comprising vertical field plates
    223.
    发明授权
    A method and a structure for enhancing electrical insulation and dynamic performance of MIS structures comprising vertical field plates 有权
    一种用于增强包括垂直场板的MIS结构的电绝缘和动态性能的方法和结构

    公开(公告)号：EP2466629B1

    公开(公告)日：2017-10-11

    申请号：EP11193548.2

    申请日：2011-12-14

    Applicant: STMicroelectronics Srl

    Inventor： Borzi, Anna ,  Coccorese, Corrado ,  Morale, Giuseppe ,  Repici, Domenico

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/40

    CPC classification number: H01L29/4236 ,  H01L21/31658 ,  H01L21/32105 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

    Abstract: A method of forming an MIS (metal-insulator-semiconductor) structure, the method comprising: forming a first semiconductor electrode in a cavity formed in a crystalline semiconductor region by depositing a first silicon containing layer provided with an increased oxidation rate relatively to an exposed surface of said crystalline semiconductor region in said cavity and depositing a second silicon containing layer above said silicon containing layer with a different oxidation rate relatively to said silicon containing layer, said first semiconductor electrode being electrically insulated from said crystalline semiconductor region by an insulating layer, concurrently oxidizing said exposed surface of said crystalline semiconductor region in said cavity and an exposed surface of said first semiconductor electrode so as to form a first oxide layer on said exposed surface of said first semiconductor electrode and a second oxide layer on said exposed surface of said crystalline semiconductor region and forming a second semiconductor electrode in said cavity and above said first semiconductor electrode, said second semiconductor electrode being electrically isolated from said first semiconductor electrode by said first oxide layer.

    MICRO-ELECTRO-MECHANICAL DEVICE WITH COMPENSATION OF ERRORS DUE TO DISTURBANCE FORCES, SUCH AS QUADRATURE COMPONENTS
    227.
    发明公开
    MICRO-ELECTRO-MECHANICAL DEVICE WITH COMPENSATION OF ERRORS DUE TO DISTURBANCE FORCES, SUCH AS QUADRATURE COMPONENTS 审中-公开
    与误差对干扰力，如磨边的基础部件补偿微机电器件

    公开(公告)号：EP2963387A1

    公开(公告)日：2016-01-06

    申请号：EP15172600.7

    申请日：2015-06-17

    Applicant: STMicroelectronics Srl

    Inventor： Falorni, Luca Giuseppe ,  Valzasina, Carlo ,  Carminati, Roberto ,  Tocchio, Alessandro

    IPC: G01C19/5733 ,  B81B3/00 ,  G01C19/5747

    CPC classification number: G01C19/5712 ,  B81B3/0018 ,  B81B3/0086 ,  B81B2201/025 ,  B81B2203/0163 ,  G01C19/5733 ,  G01C19/5747

    Abstract: The MEMS device (1) has a support region (11) elastically carrying a suspended mass (2) through first elastic elements (5; 30-37). A tuned dynamic absorber (3, 6) is elastically coupled to the suspended mass and configured to dampen quadrature forces acting on the suspended mass at the natural oscillation frequency of the dynamic absorber. The tuned dynamic absorber (3, 6) is formed by a damping mass (3) coupled to the suspended mass (2) through second elastic elements (6). In an embodiment, the suspended mass (2) and the damping mass (3) are formed in a same structural layer, for example of semiconductor material, and the damping mass (3) is surrounded by the suspended mass (2).

    Abstract translation: 的MEMS装置（1）具有一个支承区（11）可弹性携带通过第一弹性元件（5; 30-37）一悬挂质量（2）。 甲调谐动力吸振器（3,6）被弹性地联接到所述悬挂质量和配置为抑制作用于悬挂质量的动力吸振器的固有振荡频率的正交力。 调谐动力吸振器（3,6）是通过（6）第二弹性元件连接到所述悬挂质量（2）阻尼块（3）形成的。 在悬挂质量（2）的实施方式和阻尼块（3）形成在一个相同的结构层，半导体材料的实施例，而阻尼块（3）由所述悬挂质量（2）所包围。

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