公开(公告)号：EP3591425A1

公开(公告)日：2020-01-08

申请号：EP19183652.7

申请日：2019-07-01

Applicant: STMicroelectronics Ltd

Inventor： AMOR, Guy ,  PHILIPP, Tzvi ,  ROTH, Elan

IPC: G01S7/481 ,  G01S7/499 ,  G01S17/10

Abstract: A laser ranging system (5) includes a light source (32, 34) emitting a beam (31) of collimated light. A beam splitter (12) polarizes the beam with a first type of linear polarization. A wave plate (14) receives the beam from the beam splitter (12) and polarizes the beam with a circular polarization. A movable mirror (16) scans the beam across a target (22), receives a return beam (17) from the target, and reflects the return beam toward the wave plate (14). The wave plate polarizes the return beam with a second type of linear polarization. The beam splitter (12) receives the return beam (23) from the wave plate (14). A detector (20) detects arrival of the return beam from the beam splitter (12). A circuit (18) determines a distance to the target as a function of a time interval between emission of the beam (31) of collimated light and arrival of the return beam (23).

公开(公告)号：EP3290985A1

公开(公告)日：2018-03-07

申请号：EP17162674.0

申请日：2017-03-23

Applicant: STMicroelectronics Ltd

Inventor： SOURANI, Sason

IPC: G02B26/08 ,  G09G3/34 ,  G09G3/02 ,  H02P25/032 ,  G01D5/241

Abstract: The present invention provides a system and method for controlling operation of a resonance MEMS mirror (1901). The system and method includes activating either an in-plane or staggered MEMS mirror via sets of activation pulses applied to the MEMS mirror, detecting (1915) current at the MEMS mirror, generating a window for detecting a change in a direction of the current at the MEMS mirror, and terminating the window and the activation pulse if a change in the current direction is detected during the window. In some embodiments, two sets of activation pulses are applied to the MEMS mirror.

Abstract translation: 本发明提供了用于控制共振MEMS反射镜（1901）的操作的系统和方法。 该系统和方法包括通过施加到MEMS反射镜的激活脉冲组来激活平面内或交错的MEMS反射镜，检测（1915）MEMS反射镜处的电流，生成用于检测电流方向 MEMS反射镜，并且如果在窗口期间检测到电流方向的变化，则终止窗口和激活脉冲。 在一些实施例中，将两组激活脉冲施加到MEMS反射镜。

公开(公告)号：EP1878692B1

公开(公告)日：2011-04-20

申请号：EP06014651.1

申请日：2006-07-14

Applicant: STMicroelectronics Srl ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2272794A1

公开(公告)日：2011-01-12

申请号：EP10184071.8

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package comprising a substrate (20) and a damage-sensitive device (21), comprising a package substrate core (14) having an upper and a lower surface (14a, 14b), at least one pair of metal layers (12a, 12b, 13a, 13b) coating said upper and lower surfaces (14a, 14b) of the package substrate core (14); one pair of solder mask layers (11a, 11b) coating the outer metal layers (12a, 12b) of the at least one pair of metal layers (12a, 12b, 13a, 13b); and a plurality of vias (19) formed across the package substrate core (14) and the at least one pair of metal layers (12a, 12b, 13a, 13b) and a damage-sensitive device mounted on top of the upper solder mask layer. Advantageously, the plurality of vias (19) is substantially distributed according to a homogeneous pattern in an area (21 a) that is to be covered by the damage-sensitive device (21), a plurality of vias (19) being positioned so that the vias substantially coincide with an outline of said damage-sensitive device (21) that the semiconductor package substrate (20) is intended to support.
A method for the production of such semiconductor package substrate is also described.

Abstract translation: 一种包括基板（20）和损伤敏感装置（21）的半导体封装，包括具有上表面和下表面（14a，14b）的封装衬底芯（14），至少一对金属层（12a， 12b，13a，13b）涂覆所述封装基板芯（14）的所述上表面和下表面（14a，14b）; 一对涂覆至少一对金属层（12a，12b，13a，13b）的外金属层（12a，12b）的焊料掩模层（11a，11b） 以及形成在所述封装衬底芯（14）和所述至少一对金属层（12a，12b，13a，13b）之间的多个通孔（19）和安装在所述上焊接掩模层的顶部上的损伤敏感器件 。 有利地，多个通孔（19）根据待被损伤敏感设备（21）覆盖的区域（21a）中的均匀图案基本上分布，多个通孔（19）被定位成使得 通孔基本上与半导体封装衬底（20）旨在支撑的所述损伤敏感器件（21）的轮廓一致。 还描述了制造这种半导体封装基板的方法。

公开(公告)号：EP1884981A1

公开(公告)日：2008-02-06

申请号：EP06118420.6

申请日：2006-08-03

Applicant: STMicroelectronics Ltd (Malta)

Inventor： Formosa, Kevin

IPC: H01L21/00 ,  H01L21/68 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68336

Abstract: The present invention relates to a removable wafer expander for a die bonding equipment for singularized wafer (7) supported by flexible sticky means (8). Said removable wafer expander is provided with a first ring member (2) to be coupled with a second ring member (3) for a remote expansion of said flexible sticky means (8) comprises therebetween before the mounting of said wafer expander onto the die bonding equipment.

Abstract translation: 本发明涉及用于由柔性粘性装置（8）支撑的单晶化晶片（7）的晶片键合设备的可移除晶片扩展器。 所述可移除晶片扩展器设置有第一环构件（2），所述第一环构件与第二环构件（3）耦合，用于在所述晶片扩展器安装到管芯接合之前，所述柔性粘性构件（8）包括其间的远程扩展 设备。

公开(公告)号：EP1878692A1

公开(公告)日：2008-01-16

申请号：EP06014651.1

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package substrate (20) suitable for supporting a damage-sensitive device (21), comprising a package substrate core (14) having an upper and a lower surface (14a, 14b), at least one pair of metal layers (12a, 12b, 13a, 13b) coating said upper and lower surfaces (14a, 14b) of the package substrate core (14); one pair of solder mask layers (11a, 11b) coating the outer metal layers (12a, 12b) of the at least one pair of metal layers (12a, 12b, 13a, 13b); and a plurality of vias (19) formed across the package substrate core (14) and the at least one pair of metal layers (12a, 12b, 13a, 13b). Advantageously, the plurality of vias (19) is substantially distributed according to a homogeneous pattern in an area (21a) that is to be covered by the damage-sensitive device (21).
A method for the production of such semiconductor package substrate is also described.

Abstract translation: 一种适于支撑损伤敏感器件（21）的半导体封装衬底（20），包括具有上表面和下表面（14a，14b）的封装衬底芯（14），至少一对金属层（12a， 12b，13a，13b）涂覆所述封装基板芯（14）的所述上表面和下表面（14a，14b）; 一对涂覆至少一对金属层（12a，12b，13a，13b）的外金属层（12a，12b）的焊料掩模层（11a，11b） 以及形成在所述封装衬底芯（14）和所述至少一对金属层（12a，12b，13a，13b）之间的多个通孔（19）。 有利的是，多个通孔（19）在要被损伤敏感装置（21）覆盖的区域（21a）中根据均匀的图案基本分布。 还描述了制造这种半导体封装基板的方法。

公开(公告)号：EP1708363A2

公开(公告)日：2006-10-04

申请号：EP06111953.3

申请日：2006-03-29

Applicant: Stmicroelectronics Ltd.

Inventor： Chiskis, Alexander

IPC: H03H17/06 ,  H03H17/02

CPC classification number: H03H17/0275 ,  H03H17/0657 ,  H03H17/0664

Abstract: An interpolation filter (50) for interpolating a digital signal (x (n)) includes a cascade of template filters (40), each having an identical template transfer function A (z), which is arranged to receive and filter an input sequence representing the digital signal sampled at an input sampling rate. Ancillary circuitry is coupled to the cascade so as to produce first (y 0 (n)) and second phase outputs (y 1 (n)). A multiplexer (41) is arranged to multiplex the phase outputs in order to generate an output sequence having an output sampling rate equal to twice the input sampling rate.

Abstract translation: 用于内插数字信号（x（n））的内插滤波器（50）包括级联的模板滤波器（40），每个模板滤波器具有相同的模板传递函数A（z），其被布置为接收和过滤表示 以输入采样率采样数字信号。 辅助电路耦合到级联，以产生第一（y 0（n））和第二相输出（y 1（n））。 复用器（41）被布置为多路复用相位输出，以便产生具有等于输入采样率的两倍的输出采样率的输出序列。

公开(公告)号：EP1439398A1

公开(公告)日：2004-07-21

申请号：EP03250275.9

申请日：2003-01-16

Applicant: STMicroelectronics, Ltd.

Inventor： Ravenhill, Paul ,  Dellow, Andrew ,  Hutson, Matthew

IPC: G01R31/3185

CPC classification number: G01R31/318558 ,  G01R31/31719 ,  G01R31/318536

Abstract: A semiconductor integrated circuit has logic components for testing using scan chains. Scan chains comprise latch components. The scan chains are arranged such that any latch components for storing secret data, such as passwords or keys, are arranged in separate secure scan chains separate from the main scan chains. A security arrangement prevents access to this secure scan chains to unauthorised parties.

Abstract translation: 半导体集成电路具有用于使用扫描链进行测试的逻辑组件。 扫描链包括闩锁部件。 扫描链被布置成使得用于存储秘密数据（例如密码或密钥）的任何锁存部件被布置在与主扫描链分开的分开的安全扫描链中。 一种安全措施防止访问这个安全的扫描链到未经授权的方面。

公开(公告)号：EP1418701A1

公开(公告)日：2004-05-12

申请号：EP02257788.6

申请日：2002-11-11

Applicant: STMicroelectronics, Ltd.

Inventor： Dellow, Andrew Dellow ,  Cordero, Rodrigo

IPC: H04L9/08 ,  H04N7/167

CPC classification number: H04N21/4181 ,  G06F21/602 ,  H04L9/083 ,  H04L9/0894 ,  H04L2209/60 ,  H04N7/163 ,  H04N7/1675 ,  H04N21/63345

Abstract: A semiconductor circuit for use in a system for receiving and decrypting broadcast signals such as pay television comprises an input and stores for receiving a decryption key in two portions named mother and daughter portion. The splitting of the key into two portions allows a common main or mother portion to be sent broadcast to a large number of subscribers and for separate daughter portions to be sent to each subscriber or group of subscribers depending upon, for example, entitlements for which the subscribers have paid. The semiconductor circuit is arranged to retrieve the mother portion and a relevant daughter portion to construct a complete decryption key.

Abstract translation: 在用于接收和解密诸如付费电视之类的广播信号的系统中的半导体电路包括一个输入和存储，用于接收两部分称为母子部分的解密密钥。 将密钥分成两部分允许将普通主或母部分发送到大量订户，并且将单独的子部分发送到每个订户或订户组，这取决于例如， 用户已付款。 半导体电路被布置成检索母部分和相关的子部分以构建完整的解密密钥。

公开(公告)号：EP1376413A1

公开(公告)日：2004-01-02

申请号：EP02425415.3

申请日：2002-06-25

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd.

Inventor： Blasi, Gianluca ,  Tayal, Reenee

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  Y10S707/99933

Abstract: A computer based test bench generator (1) for verifying integrated circuits specified by models in a Hardware Description Language comprises a repository (10) storing a general set of self-checking tests applicable to the integrated circuits, means for entering behaviour data (21) of an integrated circuit model (20), means for entering configuration data (22) of the integrated circuit model and means for automatically generating test benches (30) in said Hardware Description Language, which means are configured to make a selection and setup of suitable tests from the repository according to the specified integrated circuit model, configuration and behaviour data.

Abstract translation: 一种用于验证由硬件描述语言中的模型指定的集成电路的基于计算机的测试台发生器（1）包括存储适用于集成电路的一般的一组自检测试的存储库（10），用于输入行为数据（21）的装置 集成电路模型（20）的装置，用于输入集成电路模型的配置数据（22）的装置和用于在所述硬件描述语言中自动生成测试台（30）的装置，所述装置被配置为进行适当的选择和设置 根据指定的集成电路模型，配置和行为数据从存储库进行测试。