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公开(公告)号：KR100439511B1
公开(公告)日：2004-07-09
申请号：KR1020020038792
申请日：2002-07-05
Applicant: 삼성전기주식회사
IPC: H01L21/78
CPC classification number: B81C1/00888 , B81C1/00896 , B81C2201/053
Abstract: A dicing method for a micro electro mechanical system chip, in which a high yield and productivity of chips can be accomplished, resulting from preventing damage to microstructures during a dicing process by using a photoresist or filler. The dicing method comprises the steps of spraying a liquid photoresist as a protectant of microstructures on a wafer on which the microstructures are installed, and coating the whole surface of the wafer with the photoresist (first step); heat treating the coated wafer at a predetermined temperature for a certain time to remove residual water in the sprayed photoresist and to cure the sprayed photoresist (second step); dicing the heat treated wafer (third step); and removing the photoresist (fourth step).
Abstract translation: 一种用于微机电系统芯片的切割方法，其中通过使用光致抗蚀剂或填充物防止在切割过程期间对微结构的损害，可以实现芯片的高产量和生产率。 切割方法包括以下步骤：将液体光致抗蚀剂作为微结构的保护剂喷涂在其上安装微结构的晶片上，并且用光致抗蚀剂涂覆晶片的整个表面（第一步骤）; 在预定的温度下热处理涂覆的晶片一段时间以除去喷涂的光刻胶中的残留水并固化喷涂的光刻胶（第二步）; 切割热处理过的晶片（第三步）; 并去除光刻胶（第四步）。
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公开(公告)号：KR101697802B1
公开(公告)日：2017-01-18
申请号：KR1020117027010
申请日：2010-03-19
Applicant: 브레우어 사이언스 인코포레이션
IPC: H01L21/027 , H01L21/308 , B81C1/00 , C08G61/08 , G03F7/033 , G03F7/09
CPC classification number: B81C1/00801 , B81C2201/053 , C08G61/08 , C08G2261/3324 , C08G2261/418 , G03F7/033 , G03F7/094 , H01L21/0274 , H01L21/3081 , Y10T428/31645 , Y10T428/31667 , Y10T428/31692 , Y10T428/31855 , Y10T428/31909
Abstract: 신규한조성물및 반도체및 MEMS 디바이스의제조동안보호레이어로서이러한조성물을사용하는방법이제공된다. 조성물은용매시스템에분산되거나용해된사이클로올레핀공중합체를포함하고, 산식각및 다른가공및 취급동안기판을보호하는레이어를형성하기위하여사용될수 있다. 보호레이어는광민감성또는비-광민감성일수 있고, 보호레이어아래에프라이머레이어와함께또는프라이머레이어없이사용될수 있다. 바람직한프라이머레이어는용매시스템중의염기성고분자를포함한다.
Abstract translation: 提供了在制造半导体和MEMS器件期间使用这些组合物作为保护层的新组合物和方法。 组合物包含分散或溶解在溶剂体系中的环烯烃共聚物，并且可以用于在酸蚀刻和其它加工和处理期间形成保护基材的层。 保护层可以是光敏的或非感光的，并且可以在保护层下面使用或不使用底漆层。 优选的底漆层在溶剂体系中包含碱性聚合物。
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公开(公告)号：KR1020140047552A
公开(公告)日：2014-04-22
申请号：KR1020130121139
申请日：2013-10-11
Applicant: 인피니언 테크놀로지스 아게
CPC classification number: B81C1/00825 , B81B2201/0235 , B81B2201/0257 , B81B2201/0264 , B81C1/00873 , B81C2201/017 , B81C2201/053 , H04R19/005 , H04R19/04 , H04R31/00 , H04R2201/003
Abstract: Disclosed are a method for manufacturing a MEMS device, a MEMS device, and a module including a MEMS device. According to an embodiment of the present invention, the method for manufacturing a MEMS device comprises a step of forming MEMS layers on a first main surface of a substrate; a step of forming a polymer layer on the second main surface of the substrate; and a step of forming a first opening inside the polymer layer and the substrate to make the first opening adjacent to the MEMS layers.
Abstract translation: 公开了一种用于制造MEMS器件，MEMS器件和包括MEMS器件的模块的方法。 根据本发明的实施例，MEMS器件的制造方法包括在衬底的第一主表面上形成MEMS层的步骤; 在基板的第二主表面上形成聚合物层的步骤; 以及在所述聚合物层和所述基板内部形成第一开口以制造与所述MEMS层相邻的所述第一开口的步骤。
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公开(公告)号：KR1020090049974A
公开(公告)日：2009-05-19
申请号：KR1020080028284
申请日：2008-03-27
Applicant: 인더스트리얼 테크놀로지 리서치 인스티튜트
IPC: H01L23/58
CPC classification number: B81C1/00793 , B81B7/0054 , B81B2201/0292 , B81B2207/07 , B81C1/00182 , B81C2201/053 , H01L2224/0401 , H01L2224/05548 , H01L2224/13023 , H01L2924/1461 , H01L2924/00
Abstract: 웨이퍼 레벨 센싱 패키지 및 그 제조 공정이 설명된다. 그 공정은 센싱 영역과 패드를 갖는 센싱 칩을 갖는 웨이퍼를 구비하는 단계; 웨이퍼에 스트레스 완화층을 형성하는 단계; 스트레스 완화층에 포토레지스트층을 클래드하는 단계; 개구 영역과 센싱 영역을 노출함이 없이 패드 및 스트레스 완화층의 일부를 노출하도록 포토레지스트층을 패턴하는 단계; 포토레지스트층에 의해 노출된 스트레스 완화층의 부분에 재배선 패드의 도전성 금속층을 형성하는 단계; 포토레지스트층을 제거하는 단계; 스트레스 완화층과 도전성 금속층에 리클래딩 포토레지스트층을 형성하는 단계; 재분배 패드 영역 상부의 리클래딩 포토레지스트층에 홀을 형성하는 단계; 도전성 금속층에 전기적으로 연결하기 위해 홀에 도전성 범프를 형성하는 단계를 포함한다.
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公开(公告)号：KR1020070108376A
公开(公告)日：2007-11-09
申请号：KR1020077018811
申请日：2005-12-21
Applicant: 로베르트 보쉬 게엠베하
IPC: B81B3/00
CPC classification number: B81C1/00158 , B81B2201/0264 , B81C1/00476 , B81C2201/0109 , B81C2201/053
Abstract: The invention relates to a method for producing a micromechanical membrane sensor or a membrane sensor produced by means of said method. According to the invention, the micromechanical membrane sensor comprises at least one first membrane and a second membrane arranged essentially above the first membrane. Furthermore, the micromechanical membrane sensor comprises a first cavity and a second cavity arranged essentially above the first cavity.
Abstract translation: 本发明涉及通过所述方法制造的微机械膜传感器或膜传感器的制造方法。 根据本发明，微机械膜传感器包括至少一个第一膜和基本上在第一膜上方布置的第二膜。 此外，微机械膜传感器包括基本上在第一腔上方布置的第一腔和第二腔。
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Patent Agency Ranking
公开(公告)号：KR1020070062584A
公开(公告)日：2007-06-15
申请号：KR1020077009521
申请日：2005-08-30
Applicant: 퀄컴 엠이엠에스 테크놀로지스, 인크.
CPC classification number: B81B3/0086 , B81C2201/0109 , B81C2201/014 , B81C2201/053 , G02B26/001 , G02B26/0833
Abstract: In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the microelectromechanical systems device.
Abstract translation: 在一个实施例中，本发明提供一种用于制造微机电系统装置的方法。 该方法包括制造包括具有特征机电响应的薄膜和特征光学响应的第一层，其中特征光学响应是期望的，并且特征机电响应是不希望的; 以及通过在所述微机电系统装置的启动期间至少减少其上的电荷积累来修改所述第一层的特征机电响应。
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公开(公告)号：KR1020040004768A
公开(公告)日：2004-01-16
申请号：KR1020020038791
申请日：2002-07-05
Applicant: 삼성전기주식회사
IPC: B81B7/02
CPC classification number: B81C1/00888 , B81C1/00896 , B81C2201/053
Abstract: PURPOSE: A method for dicing chips having a MEMS is provided to improve a yield rate and productivity by preventing micro structures from being broken during a dicing process. CONSTITUTION: A grid line and a shape of a wafer, which are identical to the size of a chip to be subject to a dicing process, are drawn on a non-adhesive side of a transparent tape. Then, a micro structure protecting layer is attached to an adhesive side of the transparent tape. After that, the transparent tape is attached to a wafer by matching the grid line with a dicing line of the wafer. Then, the transparent tape is cut into a predetermined size, which is larger than a size of the wafer, and the wafer is mounted on a guide ring so as to perform a dicing process. After that, the transparent tape is removed from the wafer.
Abstract translation: 目的：提供一种用于切割具有MEMS的芯片的方法，以通过在切割工艺期间防止微结构破裂来提高产率和生产率。 构成：在透明带的非粘合侧上绘制与待切割处理的芯片的尺寸相同的格栅线和晶片形状。 然后，将微结构保护层附着到透明带的粘合剂侧。 之后，通过使晶格线与晶片的切割线相匹配来将透明带附着到晶片。 然后，将透明胶带切割成大于晶片的尺寸的预定尺寸，并且将晶片安装在导向环上以进行切割处理。 之后，将透明带从晶片上取出。
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公开(公告)号：KR1020010051524A
公开(公告)日：2001-06-25
申请号：KR1020000066090
申请日：2000-11-08
Applicant: 이엠. 마이크로일레크트로닉-마린 쏘시에떼 아노님
Inventor： 울리츠,뮨츠
IPC: H01L21/306
CPC classification number: B81C1/00801 , B81C2201/053 , B81C2203/0735 , H01L24/11 , H01L24/13 , H01L2224/13099 , H01L2224/13144 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/00014
Abstract: PURPOSE: A metal film for protecting the surface of a structure formed on a semiconductor substrate is provided to protect the structure from KOH etchant, by depositing metal films including an external gold layer on the surface of the structure. CONSTITUTION: The structure is formed on the semiconductor substrate(23) made of a semiconductor base material to be etched by KOH etchant such that the semiconductor substrate has the first surface or a front surface(25) and the second surface or a back surface(27). An aluminum connection pad(31) is disposed on the first surface, made of a material that can be etched by the etchant. The metal film includes the external gold layer(43) having tolerance regarding the etchant, formed on the first surface and covering the aluminum connection pad.
Abstract translation: 目的：提供用于保护形成在半导体衬底上的结构的表面的金属膜，以通过在结构表面上沉积包括外部金层的金属膜来保护结构免受KOH腐蚀剂的影响。 结构：该结构形成在半导体衬底（23）上，该半导体衬底（23）由用KOH腐蚀剂蚀刻的半导体基底材料制成，使得半导体衬底具有第一表面或前表面（25）和第二表面或后表面 27）。 铝连接垫（31）设置在第一表面上，由可被蚀刻剂蚀刻的材料制成。 金属膜包括形成在第一表面上并覆盖铝连接焊盘的关于蚀刻剂的公差的外部金层（43）。
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239.发明公开公开(公告)号：US20240208801A1
公开(公告)日：2024-06-27
申请号：US17747879
申请日：2022-05-18
Applicant: UPBEAT TECHNOLOGY Co., Ltd
Inventor： Hsi-Wen TUNG , Hsien-Lung HO
CPC classification number: B81B3/0021 , B81C1/00182 , B81B2201/0257 , B81B2201/0285 , B81B2203/0315 , B81B2203/0353 , B81C2201/013 , B81C2201/0159 , B81C2201/053
Abstract: A MEM vibration sensor includes a substrate and a sensing-device. The substrate includes a first supporting-portion and a cavity. The sensing-device includes a first sensing-unit, a second sensing-unit, a first metal pad and a second metal pad. The first sensing-unit includes a second supporting-portion and a vibrating-portion. The second supporting-portion is located on the first supporting-portion and is connected to the first supporting-portion via a first dielectric material. The vibrating-portion is located on the cavity, and is connected with the second supporting-portion through an elastic connecting-portion. The second sensing-unit is located on the first sensing-unit and includes a sensing-portion and a third supporting-portion. The sensing-portion is located on the vibrating-portion and has a gap with the vibrating-portion. The third supporting-portion is located on the second supporting-portion, is connected to the sensing-portion, and is connected to the second supporting-portion through a second dielectric material.
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公开(公告)号：US20230382724A1
公开(公告)日：2023-11-30
申请号：US17825225
申请日：2022-05-26
Inventor： Wen-Chuan Tai , Hsiang-Fu Chen , Chia-Ming Hung , I-Hsuan Chiu , Fan Hu
CPC classification number: B81C1/00801 , B81B3/0051 , B81B2203/0127 , B81C2201/053
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.
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