公开(公告)号：EP1705973A2

公开(公告)日：2006-09-27

申请号：EP06014607.3

申请日：1996-10-23

Applicant: IBIDEN CO., LTD.

Inventor： Kawamura, Yoichiro ,  Murase, Hideki ,  Asai, Motoo

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

Abstract: A build-up multilayer printed circuit board in which an interlaminar insulating layer (2) and a conductor layer (5, 5') are alternately laminated on at least one surface of a wiring substrate (1) having a conductor circuit and a through-hole (9), and the conductor layers (5, 5') are electrically connected to each other through a viahole (7) formed in the interlaminar insulating layer (2), characterized in that a roughened layer (11) is formed on the surface of the conductor in an inner wall of the through-hole (9), and a resin filler comprising a resin and inorganic particles is filled in the through-hole (9) formed in the substrate (1).

Abstract translation: 一种积层多层印刷电路板，其中在具有导体电路和通孔的布线基板（1）的至少一个表面上交替层叠层间绝缘层（2）和导体层（5,5'）， 孔（9）和导体层（5,5'）通过形成在层间绝缘层（2）中的通孔（7）彼此电连接，其特征在于，在所述层间绝缘层 在通孔（9）的内壁中的导体表面和包含树脂和无机颗粒的树脂填料填充在形成在基板（1）中的通孔（9）中。

公开(公告)号：EP0817548B1

公开(公告)日：2006-04-05

申请号：EP96942586.7

申请日：1996-12-19

Applicant: IBIDEN CO., LTD.

Inventor： MORI, Yoji ,  KAWAMURA, Yoichiro

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T428/24917

Abstract: A printed wiring board (1) such that openings (8L) formed around a pad (12L) which is a photo-via land do not overlap a pad (12L) and the area of each of the openings (8L) around the pad (12L) is equal to that of each of the other openings (8), the amount of resin (13) with which each of the openings (8, 8L) is filled is equal to that with which each of the openings (8L) is filled over the whole wiring board (1), and the amounts of resin (13) overflowing from the openings (8, 8L) are equal to each other. The circuit pattern provided on the upper surface of an interlayer insulating layer formed on the printed wiring board can be connected to a conductor pad area without causing any defective connection, providing a highly-reliable printed wiring board.

公开(公告)号：EP1641330A1

公开(公告)日：2006-03-29

申请号：EP05108757.5

申请日：2005-09-22

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Eiki, Shunsuke, c/o Meiko Electronics Co., Ltd

IPC: H05K1/16

CPC classification number: H01G4/012 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09881

Abstract: A circuit board including a capacitor structure (3) formed on a surface (1a) of an insulating substrate (1), wherein the capacitor structure (3) includes paired linear conductive layers (3A) arranged on the surface (1a) of the insulating substrate (1), parallel to each other with a predetermined distance (G) between them, and a dielectric material (3C) filled in a groove defined by those surfaces (3B) of the paired linear conductive layers (3A) which face each other and the surface (1a) of the insulating substrate (1).

Abstract translation: 1。一种电路基板，其特征在于，在绝缘基板（1）的表面（1a）形成有电容器结构体（3），所述电容器结构体（3）具有配置在所述绝缘体表面（1a）上的成对的线状导体层 （3A）的表面（3B）所限定的凹槽中的电介质材料（3C），所述电介质材料（3C）彼此平行且具有预定距离（G） 和绝缘基板（1）的表面（1a）之间。

公开(公告)号：EP1621278A1

公开(公告)日：2006-02-01

申请号：EP04018152.1

申请日：2004-07-30

Applicant: Phoenix Precision Technology Corporation

Inventor： Hsu, Shih-Ping ,  Hu, Chu-Chin

IPC: B23K1/20 ,  H01L21/60

CPC classification number: H01L23/49816 ,  B23K3/0623 ,  B23K2201/42 ,  H01L21/4853 ,  H01L21/563 ,  H01L24/28 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K3/1216 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/3484 ,  H05K2201/09881 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface of each of the conductive pads is exposed. Next, a conductive film and a resist layer are formed in sequence on the insulating layer and the conductive pads, wherein a plurality of openings are formed in the resist layer to expose a part of the conductive film above the conductive pad. Then, a pre-soldering material is deposited over the conductive pad by stencil printing or electroplating process.

Abstract translation: 提出了一种用于预焊接材料的衬底和该衬底的制造方法。 提供具有形成有多个导电焊盘的至少一个表面的衬底。 在衬底的表面上形成绝缘层，使得每个导电焊盘的顶表面露出。 接下来，在绝缘层和导电焊盘上依次形成导电膜和抗蚀剂层，其中在抗蚀剂层中形成多个开口以将导电膜的一部分暴露在导电焊盘之上。 然后，通过模板印刷或电镀工艺在导电焊盘上沉积预焊材料。

公开(公告)号：EP1229772A4

公开(公告)日：2005-07-20

申请号：EP01948057

申请日：2001-07-17

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： SUZUMURA MASAKI ,  HASHIMOTO FUMIAKI

IPC: H05K7/20 ,  H01L23/12 ,  H05K1/02 ,  H05K1/03 ,  H05K1/05 ,  H05K3/04 ,  H05K3/20 ,  H05K3/28 ,  H05K3/38 ,  H05K3/22

CPC classification number: H05K1/056 ,  H01L2924/0002 ,  H05K1/0373 ,  H05K3/202 ,  H05K3/28 ,  H05K2201/0209 ,  H05K2201/09881 ,  Y10S428/901 ,  Y10T428/12514 ,  Y10T428/12556 ,  Y10T428/24917 ,  Y10T428/31681 ,  H01L2924/00

Abstract: A circuit board comprising a composite resin (1) and a metal plate (3) having a circuit pattern. A copper or copper alloy plate exhibiting excellent thermal conductivity is preferably employed as the metal plate. The composite resin is made of 70-95 parts by weight of inorganic filler and 5-30 parts by weight of resin composition containing a thermosetting resin and a setting agent. At least one side, joined with the composite resin, of the metal plate is subjected to surface roughening and adhesion enhancement. In the circuit board, the composite resin enters the gap between the circuit patterns, and the composite resin composition and the metal plate form a plane on the side of the metal plate where a component is mounted. Since the resin composition containing the inorganic filler is also present between the circuit patterns formed of the metal plate, the heat dissipation characteristic of the circuit board is enhanced significantly, and a circuit board suitable for an electronic apparatus containing a heat generating component, e.g. a power circuit, is produced.

Abstract translation: 本发明的电路板包括复合树脂和金属板，并且金属板形成电路图案。 金属板优选由具有优异导热性的铜或铜合金制成。 复合树脂包含70-95重量份的无机填料和5-30重量份的包含热固性树脂和硬化剂的树脂组合物。 金属板被表面粗糙化或处理以至少在与复合树脂接触的一个表面上增强粘合力。 在本发明的电路基板中，复合树脂填充电路图案之间的空间，复合树脂组合物和金属板在用于安装元件的金属板侧形成一个平面。 在本发明的电路基板中，由于含有无机填料的树脂组合物也存在于金属板的电路图案之间的空间中，其散热特性极高，因此适合作为电子设备的电路基板 包含发电部件如电源电路。

公开(公告)号：EP1549121A2

公开(公告)日：2005-06-29

申请号：EP04257925.0

申请日：2004-12-17

Applicant: TDK Corporation

Inventor： Abe, Toshiyuki ,  Suzuki, Yoshihiro ,  Katsumata, Masashi

IPC: H05K1/16 ,  H03F3/60

CPC classification number: H05K1/0265 ,  H01L2924/1423 ,  H03F3/195 ,  H03F2200/294 ,  H05K1/165 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0542

Abstract: An inductor element containing circuit board (1) of the present invention comprises a plurality of conductive layers, and a conductor having an inductor function (inductor conductor segment, 21) in one or more of the conductive layers, wherein at least part of the inductor conductor segment (21) is made thicker than other conductors disposed within the circuit board (1). The at least part of the inductor conductor segment (21) extends through an insulating layer (11-17) disposed between the conductive layers, or is embedded in the insulating layer (11-17), wherein the part of the inductor conductor segment (21) has a thickness one-half or more the thickness of the insulating layer (11-17). A power amplifier module (100) of the present invention comprises the multi-layer circuit board (1), a semiconductor amplifier fabricated in the multi-layer circuit board (1), and an impedance matching circuit coupled to the output of the semiconductor amplifier. The impedance matching circuit has a portion thereof formed of the inductor conductor segment (21).

公开(公告)号：EP1481575A2

公开(公告)日：2004-12-01

申请号：EP03743491.7

申请日：2003-03-03

Applicant: Printar Ltd.

Inventor： ZOHAR, Ron ,  MOZEL, Jacob ,  VILK, Ran

IPC: H05K3/02 ,  H01K3/10 ,  B05D5/12 ,  B05D5/00 ,  B05D3/02 ,  B05D3/00 ,  C08F2/48 ,  C08J7/06

CPC classification number: H05K3/0091 ,  H05K3/28 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/081 ,  H05K2203/1509

Abstract: A method and apparatus for applying ink, according to a soldermask pattern, to a printed circuit board (360) having elevated pads defining pad edges, the method including flooding the printed circuit board (360) with ink such that the ink advances, without climbing onto the elevated pads.

公开(公告)号：EP0800336B1

公开(公告)日：2004-09-15

申请号：EP96935417.4

申请日：1996-10-23

Applicant: IBIDEN CO., LTD.

Inventor： KAWAMURA, Yoichiro ,  MURASE, Hideki ,  ASAI, Motoo

IPC: H05K3/46

CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

公开(公告)号：EP1445996A2

公开(公告)日：2004-08-11

申请号：EP04011285.6

申请日：1996-10-23

Applicant: IBIDEN CO., LTD.

Inventor： Kawamura, Yoichiro ,  Murase, Hideki ,  Asai, Motoo

IPC: H05K3/46

CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

Abstract: A build-up multilayer printed circuit board in which an interlaminar insulating layer (2) and a conductor layer (5,5') are alternately laminated on both surfaces of a wiring substrate (1) having a conductor circuit (4,4') and a through-hole (9), and the conductor layers (5,5') are electrically connected to each other through a viahole (7) formed in the interlaminar insulating layer (2) characterized in that a resin filler (10) comprising a bisphenol type epoxy resin cured by an imidazole curing agent and inorganic particles is filled in a concave portion created on the surfaces of the wiring substrate (1) or in the through-hole (9) formed in the substrate (1).

Abstract translation: 一种积层多层印刷电路板，其中层间绝缘层（2）和导体层（5,5'）交替地层叠在具有导体电路（4,4'）的布线基板（1）的两个表面上， 和通孔（9）之间，并且导体层（5,5'）通过形成在层间绝缘层（2）中的通孔（7）彼此电连接，其特征在于树脂填料（10）包括 由咪唑固化剂和无机颗粒固化的双酚型环氧树脂填充在布线基板（1）的表面上或在基板（1）中形成的通孔（9）中形成的凹入部分中。

公开(公告)号：EP1168901A3

公开(公告)日：2003-03-26

申请号：EP01112310.6

申请日：2001-05-19

Applicant: rotra Leiterplatten Produktions- und Vetriebs-GmbH

Inventor： Opitz, Rudi Walter ,  Stuckmann, Walter Paul Fritz

IPC: H05K3/46 ,  H01F17/00

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H05K1/165 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0143 ,  H05K2203/0759

Abstract: Mehrlagen-Leiterplatten-Verbundkörper (5) mit mindestens zwei flächig übereinander angeordneten Leiterplatten (9), welche jeweils aufweisen eine elektrisch isolierende Trägerplatte (10), elektrisch leitende Leiterbahnen (11), die auf mindestens einer Seite der Trägerplatte (10) vorgesehen sind und Ausnehmungen (12), die seitlich von den Leiterbahnen (11) und zur Trägerplatte (10) hin durch die Trägerplatte (10) begrenzt werden, und mit mindestens einer zwischen den Leiterplatten (9) angeordneten Verbundfolie (14) zum Verbinden der Leiterplatten (9), wobei die zwischen den Trägerplatten (10) der jeweiligen Leiterplatten (9) angeordneten Ausnehmungen (12) im wesentlichen vollständig mit einer Kunstharz-Masse (13) ausgefüllt sind und wobei die mindestens zwei Leiterplatten (9) und die mindestens eine Verbundfolie (14) miteinander verpreßt sind.