公开(公告)号：US20180205014A1

公开(公告)日：2018-07-19

申请号：US15744063

申请日：2016-04-22

Applicant: THE INSTITUTE OF MICROELECTRONICS OF CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing LV ,  Ming LIU ,  Qi LIU ,  Shibing LONG

IPC: H01L45/00

CPC classification number: H01L45/1266 ,  G11C13/0011 ,  G11C2213/52 ,  G11C2213/79 ,  H01L21/82 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1683

Abstract: The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: forming a copper wire in a groove through a Damascus copper interconnection process, wherein the copper wire includes a lower copper electrode for growing a storage medium, and the copper wire is arranged above a first capping layer; forming a second capping layer above the copper wire; forming a hole at a position corresponding to the lower copper electrode on the second capping layer, wherein the pore is used for exposing the lower copper electrode; performing composition and a chemical combination treatment on the lower copper electrode to generate a compound barrier layer, wherein the compound barrier layer is a compound formed by the chemical combination of elements Cu, Si and N, or a compound formed by the chemical combination of elements Cu, Ge and N; and depositing a solid electrolyte material and an upper electrode on the compound barrier layer. By means of the above technical solution, the technical problem of higher injection efficiency of Cu ions in the Cu-based resistive random access memory in the prior art is solved, and the fatigue properties of the memory are improved.

公开(公告)号：US10008602B2

公开(公告)日：2018-06-26

申请号：US14436366

申请日：2012-11-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu ,  Haizhou Yin ,  Qingqing Liang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L21/02 ,  H01L21/265 ,  H01L21/308 ,  H01L21/311 ,  H01L29/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/311 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7848

Abstract: A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack.

公开(公告)号：US09997493B2

公开(公告)日：2018-06-12

申请号：US15036090

申请日：2014-06-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences ,  NATIONAL CENTER FOR ADVANCED PACKAGING (NCAP CHINA)

Inventor： Xueping Guo ,  Yuan Lu

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2224/16225 ,  H01L2924/00

Abstract: The present invention mainly relates to a 3-D packaging structure based on a flexible substrate and a method for manufacturing the same; the method comprises: providing a bendable continuous flexible substrate, determining the shape of the substrate according to the size, the quantity and the shape of dies, and making surface wiring on the substrate to allow interlayer electrical connection; welding dies that are to be packaged onto the bendable continuous flexible substrate; filling the gaps between the dies and the substrate with an underfill; bending the substrates towards the center to allow the peripheral dies to coincide in parallel with the die situated at the center, and bonding the two layers of parallel dies with a bonding adhesive. As compared with the inventions available in the prior art, the present invention makes use of a flexible substrate as a packaging substrate, which can better satisfy the demand for high density and high levels of integration in packaging to achieve miniaturization of packaging, and realizes die packaging of good compatibility and better performance.

公开(公告)号：US20180097111A1

公开(公告)日：2018-04-05

申请号：US15720913

申请日：2017-09-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/522 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/223 ,  H01L21/225

CPC classification number: H01L29/7848 ,  H01L21/2236 ,  H01L21/2253 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L23/5221 ,  H01L27/092 ,  H01L27/0925 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

公开(公告)号：US20180033699A1

公开(公告)日：2018-02-01

申请号：US15723928

申请日：2017-10-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/761

CPC classification number: H01L21/823481 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/761 ,  H01L21/762 ,  H01L21/76208 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

公开(公告)号：US20170352806A1

公开(公告)日：2017-12-07

申请号：US15539608

申请日：2014-12-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing LV ,  Ming LIU ,  Qi LIU ,  Shibing LONG

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1206 ,  H01L27/2481 ,  H01L45/00 ,  H01L45/124 ,  H01L45/141 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

Abstract: There is provided a three-terminal atomic switching device and a method of manufacturing the same, which belongs to the field of microelectronics manufacturing and memory technology. The three-terminal atomic switching device includes: a stack structure including a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M8XY6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M8XY6 channel layer, wherein the control terminal fills the vertical trench. The source terminal resistance and the drain terminal resistance are controlled by the control terminal. The invention is based on the three-terminal atomic switching device, and realizes high switching ratio characteristic, simple structure, easy integration, high density and low cost due to high non-linearity of the source-drain resistance with respect to the control terminal voltage, and thus can be used in a gated device in a cross-array structure to inhibit a crosstalk phenomenon caused by the leakage current. The three-terminal atomic switching device proposed by the invention is suitable for a planar stacked cross-array structure and a vertical cross-array structure, so as to realize high-density three-dimensional storage.

公开(公告)号：US20170331034A1

公开(公告)日：2017-11-16

申请号：US15525200

申请日：2014-12-26

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Hangbing Lv ,  Ming Liu ,  Qi Liu ,  Shibing Long

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/24 ,  H01L27/249 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608

Abstract: The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M8XY6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M8XY6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.

公开(公告)号：US20170309736A1

公开(公告)日：2017-10-26

申请号：US15368098

申请日：2016-12-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Sen HUANG ,  Xinyu LIU ,  Xinhua WANG ,  Ke WEI ,  Qilong BAO ,  Wenwu WANG ,  Chao ZHAO

IPC: H01L29/778 ,  H01L29/20 ,  H01L21/306 ,  H01L29/15 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7786 ,  H01L21/30621 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462

Abstract: A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.

公开(公告)号：US20170263452A1

公开(公告)日：2017-09-14

申请号：US15261068

申请日：2016-09-09

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yajuan SU ,  Kunpeng JIA ,  Chao ZHAO ,  Jun ZHAN ,  Heshi CAO

IPC: H01L21/02 ,  H01L21/4757 ,  H01L21/311

CPC classification number: H01L21/02527 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02568 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/31111 ,  H01L21/47573

Abstract: A method for manufacturing a two-dimensional material structure and a resultant two-dimensional material device. The method comprises steps of: forming a sacrificial FIN structure on a substrate; covering the sacrificial FIN structure with a dielectric; releasing the sacrificial FIN structure; forming a carrier FIN structure at a position for releasing the sacrificial FIN; and self-restrictedly growing two-dimensional material structure by taking the carrier FIN structure as a substrate. Utilizing the sacrificial FIN structure to implement self-restrictedly growing of the nanometer structure of the two-dimensional material results in a high precision, lower edge roughness, high yields and low process deviation as well as compatibility with the processing of CMOS large scale integrated circuits, making the method suitable for a large scale production of the two-dimensional material and related devices.

公开(公告)号：US09716175B2

公开(公告)日：2017-07-25

申请号：US14437506

申请日：2012-11-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/786 ,  H01L27/12 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions (110) on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.