公开(公告)号：EP1426872A3

公开(公告)日：2006-02-22

申请号：EP03027181.1

申请日：2003-11-27

Applicant: STMicroelectronics Ltd.

Inventor： Saha, Kaushik ,  Maiti, Srijib Narayan

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: This invention relates to a linear scalable method for computing a Fast Fourier Transform (FFT) or Inverse Fast Fourier transform (IFFT) in a multiprocessing system using a decimation in time approach. Linear scalability means, as the number of processors increases by a factor P (for example), the computational cycle reduces by exactly the same factor P. The invention comprises computing the first two stages of an N-point FFT/IFFT as a single radix-4 butterfly computation operation while implementing the remaining (log 2 N-2) stages as radix-2 operations, fusing the 3 main nested loops of each radix-2 butterfly stage into a single radix-2 butterfly computation loop, and distributing the computation of the butterflies in each stage such that each processor computes an equal number of complete butterfly calculations thereby eliminating data interdependency in the stage.

公开(公告)号：EP1378998B1

公开(公告)日：2005-09-14

申请号：EP02291700.9

申请日：2002-07-05

Applicant: STMicroelectronics SA ,  STMicroelectronics Ltd.

Inventor： Shah, Hitesh ,  Perier, Laurent

IPC: H03L1/00

CPC classification number: H03L1/00

公开(公告)号：EP1416393A1

公开(公告)日：2004-05-06

申请号：EP02257603.7

申请日：2002-11-01

Applicant: STMicroelectronics, Ltd. ,  STMicroelectronics S.r.l.

Inventor： Homewood, Mark Owen ,  Borneo, Antonio Maria

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The processing system comprises a processor for executing instructions; a stream register unit connected to supply data from the peripheral to the processor; a FIFO connected to receive data from the peripheral and connected to the stream register unit by a communication path, along which the said data can be supplied from the FIFO to the stream register unit; and a memory bus connected between the data memory and the processor, across which the processor can access the randomly accessible data.

Abstract translation: 通过通信信道（8）连接到流注册单元（5）的先​​进先出（FIFO）存储器（16）从外设接收数据。 数据通过通道从存储器提供给流寄存器单元。 存储器总线（3）连接在数据存储器和处理器之间，处理器通过该存储器总线访问随机访问的数据。 还包括以下独立权利要求：（1）处理单位; （2）流数据处理系统; 和（3）流注册。

公开(公告)号：EP1333380A1

公开(公告)日：2003-08-06

申请号：EP02250645.5

申请日：2002-01-30

Applicant: STMicroelectronics, Ltd.

Inventor： Dellow, Andrew

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A semiconductor integrated circuit (210) for use in direct memory access (DMA) has 3 sources (214,215,216) which communicate with a bus (230) through a bus interface (220). A DMA access signal generator (290) is coupled to the bus interface (220) and asserts a DMA access output signal at DMA access signal pins (296,396) whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the 3 sources is thereby avoided. With targets on two separate integrated circuits (212,312), a single DMA access pin (396) can be used for the two targets (248,349), chip select signal at chip select pins (506,516) on the source integrated cicuit (210) indicate which of the two targets the DMA access is intended for.

Abstract translation: 用于直接存储器访问（DMA）的半导体集成电路（210）具有通过总线接口（220）与总线（230）通信的3个源（214,215,216）。 DMA访问信号发生器（290）耦合到总线接口（220），并且每当任何一个源需要DMA访问时，就在DMA访问信号引脚（296,396）断言DMA访问输出信号。 因此避免了对于3个源中的每一个的单独的DMA访问信号引脚的需要。 在两个独立集成电路（212,312）上的目标器件中，可以为两个目标（248,349）使用单个DMA访问引脚（396），源集成电路（210）上芯片选择引脚（506,516）处的芯片选择信号指示哪个 的DMA访问旨在的两个目标。

公开(公告)号：EP1315081A1

公开(公告)日：2003-05-28

申请号：EP01309854.6

申请日：2001-11-22

Applicant: STMicroelectronics, Ltd.

Inventor： Kurd, Tariq

IPC: G06F7/52 ,  G06F7/552

CPC classification number: G06F7/535 ,  G06F7/5525

Abstract: The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry comprises a carry save adder, and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in parallel.

Abstract translation: 本发明提供了用于执行平方根手术中的至少一个和一个除法运算电路。 所述电路包括一个进位保存加法器和进位传送加法器部分。 进位保存加法器和进位加法器繁殖部分平行布置。

公开(公告)号：EP1315079A1

公开(公告)日：2003-05-28

申请号：EP01309849.6

申请日：2001-11-22

Applicant: STMicroelectronics, Ltd.

Inventor： Kurd, Tariq

IPC: G06F7/52 ,  G06F7/552

CPC classification number: G06F7/535 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/5375 ,  G06F7/5525 ,  G06F2207/5528

Abstract: The invention provides circuitry for carrying out an arithmetic operation requiring a plurality of iterations. The circuitry comprises N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry comprises at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.

Abstract translation: 本发明提供用于执行需要多次迭代的算术运算的电路。 该电路包括一组相继布置的N组迭代电路，使得迭代电路组中的至少一个接收来自迭代电路组之前的一组的输出。 迭代电路组中的每一个包括至少一个加法器部分，其中全加器由迭代电路组之一中的至少一个部分提供，并且迭代电路组中的后一组中的第二部分。

公开(公告)号：EP1271783A2

公开(公告)日：2003-01-02

申请号：EP02013243.7

申请日：2002-06-17

Applicant: STMicroelectronics Ltd.

Inventor： Bal, Ankur

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17736 ,  H03K19/17744

Abstract: A structure for simplifying the programmable memory to logic interface in FPGAs is proposed. The interface is such that it isolates the general purpose routing architecture for intra-PLB (Programmable Logic Blocks) routing from the RAM address, data and control lines. The programmable logic blocks and the input-output resources of the FPGA access the embedded memory or RAM using dedicated direct interconnects. A major part of these direct interconnects surface from programmable logic blocks in vicinity of the RAM. The rest run between the input-output (IO) pads/routing and the RAM blocks. A dedicated bus-routing architecture is provided to club the memories to emulate larger RAM blocks. This bus routing is devoted to interconnection among RAM blocks and is isolated from the PLB routing resources.

Abstract translation: 一种用于简化可编程存储器，以在FPGA中逻辑接口结构的提议。 被检查的接口做了它分离为帧内PLB（可编程逻辑块）从RAM地址，数据和控制线路由通用路由架构。 可编程逻辑块和FPGA的输入 - 输出资源使用专用的直接互连访问嵌入式存储器或RAM。 论文直接互连的主要部分从可编程逻辑块在RAM的附近表面。 输入 - 输出（IO）垫/路由和RAM块之间的其余运行。 专用总线的路由架构被提供给俱乐部的记忆来模拟较大RAM块。 该总线路由是专门RAM块之间的互连，并从PLB布线资源隔离。

公开(公告)号：EP1241788A1

公开(公告)日：2002-09-18

申请号：EP01302299.1

申请日：2001-03-13

Applicant: STMicroelectronics, Ltd.

Inventor： Dellow, Andrew

IPC: H03K23/66 ,  H03K23/68 ,  H03K21/10

CPC classification number: H03K23/68 ,  H03K21/10 ,  H03K23/66

Abstract: A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs (A,B) adjacent such that one output is equal to the other delayed by one clock period. The outputs (A,B) are passed to a multiplexer (6) via further logic, the multiplexer selecting one of two inputs (X,Y) depending on whether a clock is high or low. Program logic (40) is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively "deleting" the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an "even" mark space ratio.

Abstract translation: 数字分频器具有单个循环移位器寄存器，其加载可变长度的位序列并且具有相邻的两个输出（A，B），使得一个输出等于延迟一个时钟周期的另一个输出。 输出（A，B）经由另外的逻辑被传送到多路复用器（6），多路器根据时钟是高还是低选择两个输入（X，Y）中的一个。 提供程序逻辑（40），使得通过检测0和1之间的位序列的变化，并且当检测到改变时选择性地“删除”前半个时钟周期，电路可配置为奇数，偶数或者半整数除法。 这允许偶数，奇数或半整数时钟分频与“偶数”标记空间比。

公开(公告)号：EP1209687A3

公开(公告)日：2002-09-18

申请号：EP01127859.5

申请日：2001-11-22

Applicant: STMicroelectronics Ltd.

Inventor： Dubey, Prashant

IPC: G11C11/41 ,  G11C11/418 ,  G11C11/419 ,  G06F17/50

CPC classification number: G11C11/418 ,  G11C11/41 ,  G11C11/419

Abstract: This invention relates to a synthesizable, synchronous static RAM comprising custom built memcells and a semi-custom IO / precharge section in form of bit slice, a semi-custom built decoder connected to said bit slice and a semi-custom built control clock generation section, which is connected to said semi-custom built decoder and IO section. The arrangement being such as to provides high speed access, easy testability and asynchronous initialization capabilities while reducing design time in a size that is significantly smaller than existing semi custom or standard cell base memory design.

公开(公告)号：EP1209687A2

公开(公告)日：2002-05-29

申请号：EP01127859.5

申请日：2001-11-22

Applicant: STMicroelectronics Ltd.

Inventor： Dubey, Prashant

IPC: G11C11/41 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/41 ,  G11C11/419

Abstract: This invention relates to a synthesizable, synchronous static RAM comprising custom built memcells and a semi-custom IO / precharge section in form of bit slice, a semi-custom built decoder connected to said bit slice and a semi-custom built control clock generation section, which is connected to said semi-custom built decoder and IO section. The arrangement being such as to provides high speed access, easy testability and asynchronous initialization capabilities while reducing design time in a size that is significantly smaller than existing semi custom or standard cell base memory design.

Abstract translation: 本发明涉及一种可合成的同步静态RAM，其包括定制的内存单元和位片形式的半定制IO /预充电部分，连接到所述位片的半定制内置解码器和半定制内置控制时钟生成部分 ，其连接到所述半定制内置解码器和IO部分。 这种安排是提供高速访问，易于测试和异步初始化功能，同时减少了设计时间，其尺寸明显小于现有的半定制或标准单元基础存储器设计。