公开(公告)号：US20090255722A1

公开(公告)日：2009-10-15

申请号：US12213975

申请日：2008-06-26

Applicant: Suk Won Lee ,  Chang Gun Oh ,  Mi Sun Hwang

Inventor： Suk Won Lee ,  Chang Gun Oh ,  Mi Sun Hwang

IPC: H01R12/04 ,  H05K3/00

CPC classification number: H05K3/421 ,  H05K1/116 ,  H05K3/108 ,  H05K2201/09545 ,  H05K2201/09563 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: This invention relates to a printed circuit board having a landless via hole, including a circuit pattern formed on a via made of a first metal and having a line width smaller than the diameter of the via hole, in which the circuit pattern includes a seed layer made of a second metal and a plating layer made of a third metal, which is different from the second metal, and to a method of manufacturing the same. In the printed circuit board, the via has no upper land, thus making it possible to finely form the circuit pattern which is connected to the via, thereby realizing a high-density circuit pattern.

Abstract translation: 本发明涉及一种具有无轨道通孔的印刷电路板，该无线通孔包括形成在由第一金属制成的通孔上并具有小于通孔直径的线宽的电路图案，其中电路图案包括种子层 由与第二金属不同的第三金属制成的第二金属和镀层制成，以及其制造方法。 在印刷电路板中，通孔没有上部焊盘，从而可以精细地形成连接到通孔的电路图案，从而实现高密度电路图案。

公开(公告)号：US20090123873A1

公开(公告)日：2009-05-14

申请号：US11938195

申请日：2007-11-09

Applicant: Eric Shrader ,  Uma Srinivasan ,  Clark Crawford ,  Scott Limb

Inventor： Eric Shrader ,  Uma Srinivasan ,  Clark Crawford ,  Scott Limb

IPC: G03F7/26 ,  H05K1/02

CPC classification number: H05K3/0082 ,  H05K3/0023 ,  H05K3/28 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2203/013 ,  H05K2203/0191 ,  H05K2203/0551 ,  H05K2203/0783

Abstract: A method for masking regions of photoresist in the manufacture of a soldermask for printed circuit boards is disclosed. Following application of photoresist over patterned traces on a substrate, a sheet-like thin film is applied over the photosensitive material. The thin film may adhere to the photosensitive material by way of the adhesive state of the photosensitive material or by way of an adhesive applied to the photosensitive material or the thin film or carried by the thin film. Digital mask printing may proceed on the surface of the thin film. The photosensitive material may then be exposed through the printed photomask, the thin film (with photomask) removed, and the photosensitive material developed.

Abstract translation: 公开了一种在制造用于印刷电路板的焊接掩模时掩蔽光致抗蚀剂区域的方法。 在基板上的图案化迹线上施加光致抗蚀剂之后，将片状薄膜施加在感光材料上。 薄膜可以通过感光材料的粘合状态或通过施加到感光材料或薄膜上的粘合剂或由薄膜承载的粘合剂粘附到感光材料上。 数字掩模印刷可以在薄膜的表面上进行。 然后可以通过印刷的光掩模曝光感光材料，除去薄膜（带有光掩模），并且感光材料显影。

公开(公告)号：US20080055872A1

公开(公告)日：2008-03-06

申请号：US11928397

申请日：2007-10-30

Applicant: Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K7/02

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

公开(公告)号：US20070148970A1

公开(公告)日：2007-06-28

申请号：US11319874

申请日：2005-12-27

Applicant: Ting-Hao Lin ,  Chih-Wei Lee

Inventor： Ting-Hao Lin ,  Chih-Wei Lee

IPC: H01L21/44

CPC classification number: H05K3/427 ,  H05K3/062 ,  H05K3/243 ,  H05K2201/09545

Abstract: A method of fabricating circuitry without conductive circles has steps of providing a plate with multiple apertures defined therein, the plate and inner walls of the apertures are coated with a copper layer; the copper layers are coated with a photoresist layer, which is then covered with a protective film; partly removing the photoresist layer at the apertures; removing the protective film to expose the photoresist layer; electroplating the inner walls of the apertures with copper; exposing and developing the photoresist layers; and finally, etching the copper layers to form a circuit pattern without any conductive circles.

Abstract translation: 制造没有导电圆的电路的方法具有提供其中限定有多个孔的板的步骤，所述孔的板和内壁涂覆有铜层; 铜层被涂覆有光致抗蚀剂层，然后用保护膜覆盖; 部分地在孔处除去光致抗蚀剂层; 去除保护膜以暴露光致抗蚀剂层; 用铜电镀孔的内壁; 曝光和显影光刻胶层; 最后，蚀刻铜层以形成没有任何导电圆的电路图案。

公开(公告)号：US5537740A

公开(公告)日：1996-07-23

申请号：US561533

申请日：1995-11-22

Applicant: Masaharu Shirai ,  Shuhei Tsuchita

Inventor： Masaharu Shirai ,  Shuhei Tsuchita

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/40 ,  H05K3/42 ,  H05K3/10

CPC classification number: H05K1/116 ,  H05K3/421 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09581 ,  H05K2203/135 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/0094 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4644 ,  Y10T29/49165

Abstract: A blind hole extending from upper or surface wiring of a printed circuit board to inner or lower wiring, and having an opening larger than the bottom, is formed on a substrate, and a conductor pattern is formed on the bottom and the internal wall of the blind hole to connect the inner wiring with the surface wiring.

Abstract translation: 在基板上形成有从印刷电路板的上部或表面布线延伸到内部或下部布线并且具有比底部大的开口的盲孔，并且在底部和内壁上形成导体图案 盲孔将内部接线与表面接线连接。

公开(公告)号：US4856184A

公开(公告)日：1989-08-15

申请号：US202621

申请日：1988-06-06

Applicant: Wallace D. Doeling

Inventor： Wallace D. Doeling

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09545 ,  H05K3/427 ,  H05K3/4652 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board is fabricated from a substrate of dielectric material having at least one run of conductive material adhered to one surface thereof. A second substrate of dielectric material is bonded to the one surface of the first substrate so as to cover the run of conductive material. A hole is formed through the first and second substrates and intercepts the run of conductive material. Conductive material is introduced into the hole and establishes electrically conductive contact with the run of conductive material. The diameter of the hole is at least as great as the width of the run of conductive material where it is intercepted by the hole.

Abstract translation: 电路板由介电材料的基底制成，其具有粘附到其一个表面上的至少一行导电材料。 电介质材料的第二基片结合到第一基片的一个表面，以覆盖导电材料的行程。 通过第一和第二基板形成一个孔，并拦截导电材料的行程。 将导电材料引入到孔中并与导电材料的行程建立导电接触。 孔的直径至少与导电材料的穿过孔的宽度一样大。

公开(公告)号：US4610756A

公开(公告)日：1986-09-09

申请号：US513337

申请日：1983-07-13

Applicant: Jean-Paul Strobel

Inventor： Jean-Paul Strobel

IPC: H05K3/06 ,  H05K1/11 ,  H05K3/10 ,  H05K3/34 ,  H05K3/42 ,  C23F1/02 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: H05K3/427 ,  H05K1/116 ,  H05K2201/09545 ,  H05K2203/044 ,  H05K2203/0723 ,  H05K3/062 ,  H05K3/108 ,  H05K3/3468 ,  Y10T29/49165

Abstract: The printed circuit board is produced without soldering lands around the contacting, supporting or interconnecting holes of a simple faced, double-faced or multilayer circuit.The inner wall of the hole is covered with a copper layer which extends only until the free surface of the naked board, i.e. levels that surface, or does not fully extend until this level. The said layer is covered with a tin-lead metallisation layer which serves as a soldering link element. The solder mounts towards the wire or pin of the soldered component but does not touch nor spoil the free, insulating surface of the support.One necessary condition of the making process of the board is the precise, clean, proper and sharp drilling of the holes.

Abstract translation: 印刷电路板在简单的面对，双面或多层电路的接触，支撑或互连孔周围没有焊接区域生产。 孔的内壁被铜层覆盖，铜层仅延伸到裸板的自由表面，即表面的水平，或者不完全延伸到该水平。 所述层被用作焊接连接元件的锡铅金属化层覆盖。 焊料朝向焊接部件的导线或销钉安装，但不会接触或破坏支撑件的自由绝缘表面。 板的制造过程的一个必要条件是孔的精确，清洁，适当和尖锐的钻孔。

公开(公告)号：US20240030580A1

公开(公告)日：2024-01-25

申请号：US18331946

申请日：2023-06-09

Applicant: Innolux Corporation

Inventor： Chen-Lin Yeh ,  Yan-Zheng Wu ,  Yung-Wei Chen

IPC: H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  H05K3/06 ,  H05K3/42 ,  H05K3/36

CPC classification number: H01P3/081 ,  H01P11/003 ,  H05K1/0243 ,  H05K3/06 ,  H05K3/423 ,  H05K3/368 ,  H05K2201/10151 ,  H05K2201/10196 ,  H05K2201/10098 ,  H05K2201/09545 ,  H05K2201/09618 ,  H05K2201/09609 ,  H05K3/0029

Abstract: An electronic device includes a glass substrate, a first metal layer, a second metal layer, and a third metal layer. The glass substrate includes a first surface, a second surface corresponding to the first surface, and at least two first through holes. The first through hole includes a third surface, and the third surface is connected to the first surface and the second surface. A first conductive layer is disposed on the first surface. A second conductive layer is disposed on the second surface. A third conductive layer is disposed on the third surface and is electrically connected to the first conductive layer and the second conductive layer. The first through hole has a major axis and a minor axis in a top view direction. A method of manufacturing the electronic device is also included.

公开(公告)号：US20240008177A1

公开(公告)日：2024-01-04

申请号：US17857055

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Kok Hou TEH

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K1/112 ,  H05K1/0296 ,  H05K3/4038 ,  H05K2201/09545

Abstract: The present disclosure is directed to a printed circuit board having a first surface and providing a signal pathway using a plurality of plated through hole (PTH) vias including a first set of PTH vias having a first PTH via coupled to a second PTH via and a first vertical separator being configured therebetween, with the first vertical separator extending a first depth from the first surface, and a second set of PTH vias having a third PTH via coupled to a fourth PTH via and a second vertical separator being configured therebetween, with the second vertical separator extending a second depth from the first surface, and a connector trace coupling the second PTH via to the third PTH via being positioned at a third depth from the first surface, for which the third depth is less than the first depth or the second depth.

公开(公告)号：US20230345634A1

公开(公告)日：2023-10-26

申请号：US17726235

申请日：2022-04-21

Applicant: Dell Products L.P.

Inventor： Chang-Kai Chu ,  Chang-Hsien Chen ,  Bhyrav Mutnury

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K1/115 ,  H05K3/4038 ,  H05K2201/09545

Abstract: An information handling system includes a printed circuit board having a signal via fabricated through the printed circuit board. The signal via includes a conductive metal plating. The signal via also includes first and second via portions. The first via portion is connected to a first trace of a differential pair. The second via portion is connected to a second trace of the differential pair. The first and second via portions are formed in the conductive metal plating.