公开(公告)号：WO2013061313A1

公开(公告)日：2013-05-02

申请号：PCT/IB2012/055982

申请日：2012-10-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： LOSA, Stefano ,  PEZZUTO, Raffaella ,  CAMPEDELLI, Roberto ,  AZPEITIA URQUIA, Mikel ,  PERLETTI, Matteo ,  ESPOSITO, Luigi

IPC: B81C1/00

CPC classification number: H01L21/02178 ,  B81B7/0032 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00595 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2201/053 ,  H01L21/0228

Abstract: A method for manufacturing a protective layer (25) for protecting an intermediate structural layer (22) against etching with hydrofluoric acid (HP), the intermediate structural layer (22) being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminium oxide, by atomic layer deposition, on the intermediate structural layer (22); performing a thermal crystallization process on the first layer of aluminium oxide, forming a first intermediate protective layer (25a),- forming a second layer of aluminium oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallisation process on the second layer of aluminium oxide, forming a second intermediate protective layer (25b) and thereby completing the formation of the protective layer (25). The method for forming the protective layer (25) can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.

Abstract translation: 一种用于制造用于保护中间结构层（22）以防止用氢氟酸（HP）蚀刻的保护层（25）的方法，所述中间结构层（22）由可被氢氟酸蚀刻或损坏的材料制成， 该方法包括以下步骤：通过原子层沉积在中间结构层（22）上形成第一氧化铝层; 在第一氧化铝层上进行热结晶处理，形成第一中间保护层（25a）， - 通过原子层沉积形成第二层氧化铝，在第一中间保护层上方; 以及对所述第二氧化铝层进行热结晶处理，形成第二中间保护层（25b），从而完成所述保护层（25）的形成。 形成保护层（25）的方法可以用于例如陀螺仪或加速度计等惯性传感器的制造步骤。

公开(公告)号：WO2012090188A1

公开(公告)日：2012-07-05

申请号：PCT/IB2011/056033

申请日：2011-12-30

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: A61F9/08

CPC classification number: A61F2/14 ,  A61F2/148 ,  A61F9/08 ,  A61F2250/0002 ,  A61N1/0543 ,  A61N1/36 ,  A61N1/36046

Abstract: A retinal prosthesis including an electronic stimulation unit (40) housed inside an eye and including: a plurality of electrodes (62); an electronic control circuit (92, 102), which is electrically connected to the electrodes and supplies to the electrodes electrical stimulation signals designed to stimulate a portion of a retina of the eye; and a local antenna (114) connected to the electronic control circuit. The retinal prosthesis further includes an electromagnetic expansion (35) housed inside the eye and formed by a first expansion antenna (44) and a second expansion antenna (46) electrically connected together, the first expansion antenna being magnetically or electromagnetically coupled to an external antenna (38), the second expansion antenna being magnetically or electromagnetically coupled to the local antenna, the electromagnetic expansion moreover receiving an electromagnetic supply signal transmitted by the external antenna and generating a corresponding replica signal.

Abstract translation: 一种视网膜假体，包括容纳在眼睛内的电子刺激单元（40），包括：多个电极（62）; 电子控制电路（92,102），其电连接到电极并向电极提供设计成刺激眼睛的视网膜的一部分的电刺激信号; 以及连接到电子控制电路的本地天线（114）。 视网膜假体还包括容纳在眼睛内并由电连接在一起的第一扩展天线（44）和第二扩展天线（46）形成的电磁膨胀（35），第一扩展天线被磁性或电磁耦合到外部天线 （38），所述第二扩展天线与所述本地天线进行磁或电磁耦合，所述电磁膨胀还接收由所述外部天线发送的电磁供给信号并产生对应的复制信号。

公开(公告)号：WO2012084845A1

公开(公告)日：2012-06-28

申请号：PCT/EP2011/073270

申请日：2011-12-19

Applicant: STMICROELECTRONICS S.R.L. ,  STROPPA, Alberto ,  SPINI, Claudio ,  ADRAGNA, Claudio

Inventor： STROPPA, Alberto ,  SPINI, Claudio ,  ADRAGNA, Claudio

IPC: H02M3/337

CPC classification number: H02M3/33507 ,  H02M3/3376 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A control device for a switching mode DC-DC converter, the converter comprising at least a half-bridge with at least first (Q1) and second (Q2) switches connected between an input voltage (Vin) and a reference voltage. The converter further comprises a transformer (20) with a primary coupled with the center point (HB) of the half -bridge and a secondary (22) coupled with a load (Load). The control device comprises an error detector (2) configured to determine an error signal (Se) between a first signal (Vout1) representative of the voltage (Vout) across the load and a first reference signal (Vref2) and a frequency controller (100) configured to increase the switching frequency of the half -bridge when the error signal (Se) is kept below a second signal (Vrefl).

Abstract translation: 一种用于开关模式DC-DC转换器的控制装置，所述转换器至少包括连接在输入电压（Vin）和参考电压之间的至少第一（Q1）和第二（Q2）开关的半桥。 该转换器还包括具有与半桥的中心点（HB）初级耦合的变压器（20）和与负载（负载）耦合的次级（22）。 控制装置包括误差检测器（2），其被配置为确定表示负载之间的电压（Vout）的第一信号（Vout1）与第一参考信号（Vref2）和频率控制器（100）之间的误差信号（Se） ）被配置为当误差信号（Se）保持低于第二信号（Vrefl）时增加半桥的开关频率。

公开(公告)号：WO2012084295A1

公开(公告)日：2012-06-28

申请号：PCT/EP2011/068359

申请日：2011-10-20

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  MURARI, Bruno

Inventor： PAGANI, Alberto ,  MURARI, Bruno

IPC: G01N27/20 ,  G01N33/38 ,  G01L1/18

CPC classification number: G01N27/00 ,  G01L1/26 ,  G01M5/0083

Abstract: Device (100) for detecting and monitoring local parameters within a solid structure (300). The device comprises an integrated detection module (1) made on a single chip, having an integrated functional circuitry portion (16) comprising at least one integrated sensor (10) and an integrated antenna (11), and electromagnetic means (2) for transmitting/receiving signals and energy exchange. The integrated functional circuitry portion (16) comprises a functional surface (18) facing towards the outside of the chip. A passivation layer (15) is arranged to completely cover at least the functional surface (18), so that the integrated detection module (1) is entirely hermetically sealed and galvanically insulated from the surrounding environment. The integrated antenna (11), the electromagnetic means (2) and the remote antenna (221) are operatively connected wirelessly through magnetic or electromagnetic coupling.

Abstract translation: 用于检测和监测固体结构（300）内的局部参数的装置（100）。 该装置包括在单个芯片上制成的集成检测模块（1），其具有包括至少一个集成传感器（10）和集成天线（11）的集成功能电路部分（16），以及电磁装置（2） /接收信号和能量交换。 集成功能电路部分（16）包括面向芯片外部的功能表面（18）。 钝化层（15）布置成完全覆盖至少功能表面（18），使得集成检测模块（1）完全被气密密封并与周围环境电隔离。 集成天线（11），电磁装置（2）和远程天线（221）通过磁或电磁耦合无线地可操作地连接。

公开(公告)号：WO2012084207A1

公开(公告)日：2012-06-28

申请号：PCT/EP2011/006449

申请日：2011-12-20

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: H01L23/522

CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention in a single structure combines a pad comprising a connection terminal suitable for connecting the circuit elements integrated in a chip to circuits outside of the chip itself and at least one condenser. By combining a connection pad and a condenser in a single structure it is possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the condenser itself. In this way, the costs and size of the chip can be reduced.

Abstract translation: 本发明的单一结构组合了包括适于将集成在芯片中的电路元件连接到芯片本身外部的电路的连接端子和至少一个冷凝器的焊盘。 通过在单一结构中组合连接焊盘和冷凝器，可以减少芯片的总面积，否则由于冷凝器本身的存在，否则常见的集成电路将会更大。 以这种方式，可以降低芯片的成本和尺寸。

公开(公告)号：WO2012072726A1

公开(公告)日：2012-06-07

申请号：PCT/EP2011/071480

申请日：2011-12-01

Applicant: STMICROELECTRONICS S.R.L. ,  ZUFFADA, Maurizio ,  POZZONI, Massimo ,  CONTINI, Angelo

Inventor： ZUFFADA, Maurizio ,  POZZONI, Massimo ,  CONTINI, Angelo

IPC: H03F3/30 ,  H03F1/22 ,  H03F3/24 ,  H03F3/217 ,  H03F3/45 ,  H04B10/155 ,  H03K19/0185

CPC classification number: G02F1/0121 ,  G02B6/1225 ,  G02B2006/12142 ,  G02B2006/12145 ,  G02F1/0327 ,  G02F1/225 ,  G02F2001/212 ,  H03F1/22 ,  H03F1/223 ,  H03F3/2171 ,  H03F3/245 ,  H03F3/3001 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2200/45 ,  H03F2200/516 ,  H03F2203/30099 ,  H03F2203/30132 ,  H03K19/018528 ,  H04B10/532 ,  H04B10/616

Abstract: A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).

Abstract translation: 驱动器电路可以包括第一节点（VA）和第一电路，用于在第一电源电压（Vdd1）和地之间的驱动器切换期间在第一节点（VA）上产生输入信号（VIN）的反相副本， 反转副本具有基于大于第一电源电压（Vdd1）的参考电压（Vref）的阈值电压值。 驱动器电路可以包括由参考电压（Vref）控制并耦合在第二电源电压（Vdd2）和第一节点之间的共源共栅级（M3），延迟电路（D）以产生延迟复制 输入信号（VIN），放大器和开关网络（M5，M6），用于将有源负载晶体管（M9）的控制端子耦合到参考电压（Vref）中的一个或接地，基于输入 信号（VIN）。

公开(公告)号：WO2011101393A1

公开(公告)日：2011-08-25

申请号：PCT/EP2011/052319

申请日：2011-02-16

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: H01L23/544

CPC classification number: G01R31/275 ,  G01R31/2853 ,  H01L21/76898 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A testing system for carrying out electrical testing of at least a through via (10) extending, at least in part, through a substrate (3) of a body (2) of semiconductor material and having a first end (10b) buried within the substrate (3) and not accessible from the outside of the body (2). The testing system has an electrical test circuit (22) integrated in the body (2) and electrically coupled to the through via (10) and to electrical-connection elements (8) carried by the body (2) for electrical connection towards the outside; the electrical test circuit (22) has a buried microelectronic structure (28) integrated in the substrate (3) so as to be electrically coupled to the first end (10b) of the through via (10), thereby closing an electrical path within the substrate (3) and enabling detection of at least one electrical parameter of the through via (10) through the electrical-connection means (8).

Abstract translation: 至少一个至少部分通过半导体材料的主体（2）的基板（3）延伸的通孔（10）进行电气测试的测试系统，并且具有埋在该半导体材料的第一端（10b）内的第一端 基板（3）并且不能从主体（2）的外部接近。 测试系统具有集成在主体（2）中并电耦合到通孔（10）的电测试电路（22）和由主体（2）承载的电连接元件（8），用于电连接到外部 ; 电测试电路（22）具有集成在基板（3）中的埋入微电子结构（28），以便电连接到通孔（10）的第一端（10b），从而封闭通孔 基板（3），并且能够通过电连接装置（8）检测通孔（10）的至少一个电参数。

公开(公告)号：WO2011073853A1

公开(公告)日：2011-06-23

申请号：PCT/IB2010/055632

申请日：2010-12-07

Applicant: STMICROELECTRONICS S.R.L. ,  ITALIA, Alessandro ,  DIMARTINA, Salvatore ,  IPPOLITO, Calogero Marco ,  PALMISANO, Giuseppe

Inventor： ITALIA, Alessandro ,  DIMARTINA, Salvatore ,  IPPOLITO, Calogero Marco ,  PALMISANO, Giuseppe

IPC: H03B5/12 ,  H03B1/00

CPC classification number: H03B5/1243 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1268 ,  H03B5/1296 ,  H03B2200/0038 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/0266 ,  Y10T29/49117

Abstract: Circuit (1) of a voltage controlled oscillator comprising: - a bridge structure including two cross-coupled transistors of N type (M 3 , M 4 ) and two cross-coupled transistors of P type (M 5 , M 6 ); - a current mirror (3) connected to the two cross-coupled transistors of N type (M 3 , M 4 ) and arranged to generate a bias current (I B ) for the circuit (1); - an LC resonator (2) placed in parallel between the two cross-coupled transistors of N type (M 3 , M 4 ) and the two cross-coupled transistors of P type (M 5 , M 6 ). The circuit (1) is characterised in that the LC resonator (2) comprises: two pairs of differential inductors (L 1 , L 2 ) mutually coupled by means of a mutual inductance coefficient (M), each pair comprising a first inductor (L 1 ) arranged on a respective branch (10a) of an external loop, and a second inductor (L 2 ) arranged on a respective branch (12a) of an internal loop; a first varactor (C v33 ) connected to a common node (A) and to a first branch (12a) of the internal loop; a second varactor (C v33 ) connected to the common node (A) and to a second branch (12a) of the internal loop.

Abstract translation: 压控振荡器的电路（1）包括： - 包括N型（M3，M4）的两个交叉耦合晶体管和P型（M5，M6）的两个交叉耦合晶体管的桥结构; - 连接到N型（M3，M4）的两个交叉耦合晶体管并被布置成产生用于电路（1）的偏置电流（IB））的电流镜（3）。 - 平行放置在N型（M3，M4）的两个交叉耦合晶体管和P型（M5，M6）的两个交叉耦合晶体管之间的LC谐振器（2）。 电路（1）的特征在于，LC谐振器（2）包括：通过互感系数（M）相互耦合的两对差分电感器（L1，L2），每对包括布置在第一电感器（L1） 在外部环路的相应分支（10a）上，以及布置在内部环路的相应分支（12a）上的第二电感器（L2） 连接到公共节点（A）和内部回路的第一分支（12a）的第一变容二极管（Cv33） 连接到公共节点（A）和第二分支（12a）的第二变容二极管（Cv33）。

公开(公告)号：WO2011063974A1

公开(公告)日：2011-06-03

申请号：PCT/EP2010/007185

申请日：2010-11-26

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  ROSSI, Sandro

Inventor： RICOTTI, Giulio ,  ROSSI, Sandro

IPC: H03K3/355

CPC classification number: H03K3/355

Abstract: It is described a driving circuit (1) having at least one output terminal (OUT) connected to an ultrasonic pulse generator circuit and providing thereto with an output voltage (Vout), characterized in that it comprises at least one first portion (2A) connected to a first voltage reference (VPH) and including at least one first output transistor (MOP) being inserted between the first voltage reference (VPH) and the output terminal (OUT), such a first portion (2A) further comprising: at least one first high voltage comparator (3A) being connected to said output terminal (OUT) and to a first threshold voltage reference (VTHP), at least one first start-up circuit (4A) being controlled by a first setting signal (SETP); at least one first switching ON /OFF circuit (5A) being connected at its input to the first start-up circuit (4A), in correspondence with a first internal circuit node (XP), and to the first high voltage comparator (3A), in correspondence with a second internal circuit node (YP), and at its output to a control terminal of the first output transistor (MOP); the first start-up circuit (4A) providing a switching on signal (ONA) to the first switching on/ off circuit (5A) while the high voltage comparator (3A) provides a switching off signal (OFFA) to the first switching on/ off circuit (5A) which causes the switching off of the output transistor (MOP), the high voltage comparator (3A) generating the switching off signal (OFFA) when the output voltage (Vout) reaches a first desired supply voltage value which depends on the value of the first threshold voltage reference (VTHP).

Abstract translation: 描述了具有连接到超声波脉冲发生器电路并向其提供输出电压（Vout）的至少一个输出端子（OUT）的驱动电路（1），其特征在于它包括至少一个连接的第一部分（2A） 至少一个第一输出晶体管（MOP）被插入在第一参考电压（VPH）和输出端子（OUT）之间，所述第一部分（2A）还包括：至少一个 第一高压比较器（3A）连接到所述输出端（OUT）和第一阈值电压基准（VTHP），至少一个第一启动电路（4A）由第一设置信号（SETP）控制; 至少一个第一开关ON / OFF电路（5A）在其输入端与第一内部电路节点（XP）相对应地连接到第一启动电路（4A），并连接到第一高电压比较器（3A） 对应于第二内部电路节点（YP），并且在其输出端与第一输出晶体管（MOP）的控制端相对应; 所述第一启动电路（4A）向所述第一开关导通/断开电路（5A）提供开启信号（ONA），同时所述高电压比较器（3A）向所述第一开关导通/断开电路提供断开信号（OFFA） 关闭电路（5A），当输出电压（Vout）达到第一期望的电源电压值时，高电压比较器（3A）产生关断信号（OFFA），导致关闭输出晶体管（MOP） 第一阈值电压基准值（VTHP）。

公开(公告)号：WO2010076687A1

公开(公告)日：2010-07-08

申请号：PCT/IB2009/055359

申请日：2009-11-26

Applicant: STMICROELECTRONICS S.R.L. ,  RICCI, Raffaele

Inventor： RICCI, Raffaele

IPC: G01R31/28

CPC classification number: G01R31/002 ,  G01R31/2849

Abstract: In order to verify robustness in regard to electrical overstresses of an electronic circuit under test (DUT), the latter is exposed to electrical overstresses (12, 14), and the behaviour thereof following upon exposure to said electrical overstresses is monitored (18). Moreover, the electrical overstress is applied to the electronic circuit (DUT) when the electronic circuit (DUT) is in its normal applicational conditions of operation. In particular, there is envisaged both the testing of the electronic circuit (DUT) in dynamic conditions by causing it to be traversed by the currents that characterize operation thereof and by exposing at least one supply line (20) of said electronic circuit under test (DUT) to electrical overstresses and the testing of said electronic circuit under test (DUT) in static conditions, without causing it to be traversed by the currents that characterize operation thereof and by exposing to electrical overstresses both the supply (20) and the input and/or output lines of said electronic circuit under test (DUT). The device (14) for generating the overstresses can be mounted on a circuit board (12), which can be coupled as daughter board to a mother board (10), on which the electronic circuit under test (DUT) is mounted.

Abstract translation: 为了验证被测电子电路（DUT）的电应力的鲁棒性，后者被暴露于电过压（12,14），并且在暴露于所述电过应力之后监视其行为（18）。 此外，当电子电路（DUT）处于其正常的操作条件下时，电应力施加到电子电路（DUT）。 特别地，设想在动态条件下通过使其由表征其操作的电流穿过电子电路（DUT）并且通过暴露所测试的所述电子电路的至少一个供应线（20）来测试电子电路（DUT） DUT）在静态条件下进行电过载和测试所测试的被测电子电路（DUT），而不会使其被表征其操作的电流穿过，并暴露于对电源（20）和输入端的电过载 /或被测电子电路的输出线（DUT）。 用于产生过应力的装置（14）可以安装在电路板（12）上，该电路板可以作为子板耦合到母板（10），母板（10）上安装有被测电子电路（DUT）。