公开(公告)号：US20170372990A1

公开(公告)日：2017-12-28

申请号：US15623943

申请日：2017-06-15

Applicant: JTEKT CORPORATION

Inventor： Naoki TANI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/49816 ,  H01L23/12 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/522 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/0271 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/10568 ,  H05K2201/2018

Abstract: A semiconductor device includes a semiconductor element, a circuit board, metal wires, and an expanding member. The circuit board has an upper surface and a lower surface opposite the upper surface. The metal wires arc formed on at least one of the upper surface and the lower surface. At least two connection terminals are formed in a terminal formation surface of the semiconductor element which is disposed so as to face the upper surface of the circuit board. The expanding member is fixed to the terminal formation surface of the semiconductor element, has a larger coefficient of linear thermal expansion than the semiconductor element, and has a size larger than the interval between adjacent two of the at least two connection terminals.

公开(公告)号：US09693449B2

公开(公告)日：2017-06-27

申请号：US14655488

申请日：2013-12-20

Applicant: MITSUBISHI MATERIALS CORPORATION

Inventor： Shuji Nishimoto ,  Yoshiyuki Nagatomo

IPC: H05K1/00 ,  H05K1/02 ,  H01L23/373 ,  C04B37/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/46 ,  H05K7/14 ,  H01L23/42 ,  H05K3/00 ,  H01L23/473

CPC classification number: H05K1/0271 ,  C04B37/021 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/407 ,  C04B2237/86 ,  H01L23/3735 ,  H01L23/42 ,  H01L23/473 ,  H01L2224/32225 ,  H05K1/0203 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/0061 ,  H05K3/248 ,  H05K3/32 ,  H05K3/465 ,  H05K7/14 ,  H05K2201/066 ,  H05K2201/09136

Abstract: A power module substrate includes an insulating layer, a circuit layer that is formed on a first surface of the insulating layer, and a metal layer that is formed on a second surface of the insulating layer, in which a first base layer is laminated on a surface of the metal layer on the opposite side of the surface to which the insulating layer is provided, and the first base layer has: a first glass layer that is formed at the interface with the metal layer; and a first Ag layer that is laminated on the first glass layer.

公开(公告)号：US20170142825A1

公开(公告)日：2017-05-18

申请号：US14938917

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Sayuri Hada ,  Hiroyuki Mori ,  Keishi Okamoto

IPC: H05K1/02 ,  G01B21/20 ,  H05K3/22 ,  G01B21/08 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/0271 ,  G01B21/08 ,  G01B21/20 ,  H05K1/0298 ,  H05K1/0313 ,  H05K3/0011 ,  H05K3/225 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/09909 ,  H05K2203/013 ,  H05K2203/163

Abstract: A method for reducing warpage on an organic substrate. The method includes: preparing an organic substrate, which includes (i) a core layer having an organic material, (ii) a first buildup layer on a front surface of the core layer, and (iii) a second buildup layer on a back surface of the core layer, measuring warpage of the organic substrate, calculating a thickness of a correction layer for reducing the warpage using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers, and forming at least one correction layer having the thickness on at least one part of surfaces of the first buildup layer and the second buildup layer. A system and an organic substrate is also provided.

公开(公告)号：US20170092635A1

公开(公告)日：2017-03-30

申请号：US15378947

申请日：2016-12-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hayato MASUBUCHI ,  Naoki KIMURA ,  Manabu MATSUMOTO ,  Toyota MORIMOTO

IPC: H01L25/18 ,  H01L27/115 ,  H05K3/30 ,  H01L23/528 ,  H05K1/02 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/18 ,  G11C5/02 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/115 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/10159 ,  Y02P70/613 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

公开(公告)号：US09609744B2

公开(公告)日：2017-03-28

申请号：US14666387

申请日：2015-03-24

Applicant: International Business Machines Corporation

Inventor： Mark K. Hoffmeyer ,  Amanda E. Mikhail ,  Arvind K. Sinha

IPC: G06F17/50 ,  H05K1/11 ,  H05K3/00 ,  H05K1/02 ,  H05K3/34 ,  H05K1/18 ,  G01R31/26

CPC classification number: H05K1/0271 ,  G01R31/26 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  G06F2217/14 ,  G06F2217/38 ,  G06F2217/40 ,  G06F2217/80 ,  H05K1/11 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/09136 ,  H05K2201/10734 ,  Y02P70/613

Abstract: Printed circuit boards (PCBs) can be designed to have dynamic warp characteristics complimentary to those of an attached component. A PCB and an attached component can be designed to dynamically warp, during a thermal excursion, in the same direction and with approximately the same magnitude of warp. Warp characteristics of the PCB and the attached component can be determined by the vertical thickness of conductor and dielectric layers, by the wiring density and number of conductor layers. Warp characteristics can also be at least partially determined by the arrangement/ordering of conductor and dielectric layers, by dimensions of a sash structure surrounding a component outline and by dimensions of a prepreg layer applied to an existing design. Such a prepreg layer can cover a portion or an entirety of one of the PCBs planar surfaces.

公开(公告)号：US20170084509A1

公开(公告)日：2017-03-23

申请号：US14946044

申请日：2015-11-19

Applicant: HongQiSheng Precision Electronics (QinHuangDao) Co.,Ltd. ,  FuKui Precision Component (Shenzhen) Co., Ltd. ,  Zhen Ding Technology Co., Ltd.

Inventor： YU-CHENG HUANG

IPC: H01L23/13 ,  H05K3/46 ,  H05K1/03 ,  H05K1/11 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L21/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2924/014 ,  H01L2924/15333 ,  H05K1/16 ,  H05K1/162 ,  H05K1/167 ,  H05K3/06 ,  H05K3/383 ,  H05K3/429 ,  H05K3/4608 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2201/09136 ,  H05K2203/0353

Abstract: A substrate includes a base layer, first and second circuit layers both coupled to the base layer, a third circuit layer, a fourth circuit layer and two solder resist layers. The first/second circuit layer defines a first/second opening. The third and fourth circuit layers are located at two sides of the first and second circuit layers. The solder resist layers cover outer faces of the third and fourth circuit layers. Each solder resist layer defines a window. The first opening is deviated from the second opening. The third and fourth circuit layers each have a portion exposed to the window to be a solder pad. The first circuit layer and the third circuit layer have a total thickness no more than that of the second circuit layer and the fourth circuit layer. A chip package with the substrate and a method for manufacturing the substrate are also provided.

公开(公告)号：US09532466B2

公开(公告)日：2016-12-27

申请号：US13658870

申请日：2012-10-24

Applicant: HAESUNG DS CO., LTD.

Inventor： Sang-min Lee ,  Soon-Chul Kwon

IPC: H05K3/10 ,  H05K3/46 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K3/4644 ,  H05K1/0271 ,  H05K3/0097 ,  H05K3/4652 ,  H05K2201/029 ,  H05K2201/09136 ,  H05K2203/0554 ,  H05K2203/1461 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a multi-layer circuit board includes: forming a first circuit layer on a first surface of a first prepreg; stacking a second prepreg on a first surface of the first circuit layer; and forming at least one of a second or a third circuit layer on at least one of a first surface of the second prepreg and a second surface opposite of the first surface of the first prepreg, wherein, in the stacking of the first prepreg, the first prepreg and the second prepreg are semi-cured.

Abstract translation: 制造多层电路板的方法包括：在第一预浸料的第一表面上形成第一电路层; 在第一电路层的第一表面上堆叠第二预浸料; 以及在所述第二预浸料的第一表面和与所述第一预浸料的第一表面相对的第二表面中的至少一个上形成第二或第三电路层中的至少一个，其中，在所述第一预浸料的堆叠中， 第一预浸料坯和第二预浸料半固化。

公开(公告)号：US20160309582A1

公开(公告)日：2016-10-20

申请号：US15101128

申请日：2015-01-06

Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.

Inventor： Katsuya TOMIZAWA ,  Tomo CHIBA ,  Meguru ITO ,  Eisuke SHIGA

IPC: H05K1/02 ,  C08J5/04 ,  H05K3/02 ,  C08J5/24 ,  H05K1/03 ,  H05K3/46

CPC classification number: H05K1/0271 ,  B32B15/08 ,  C08J5/043 ,  C08J5/24 ,  C08J2379/08 ,  C08J2465/00 ,  C08J2479/04 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/0393 ,  H05K3/022 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09136

Abstract: The present invention provides an insulating layer for printed circuit boards having a difference of within 20% between the flexural modulus at 25° C. and the flexural modulus under heat at 250° C.

Abstract translation: 本发明提供了一种用于印刷电路板的绝缘层，其在25℃下的挠曲模量与在250℃下加热时的挠曲模量之间的差异在20％以内。

公开(公告)号：US20160234929A1

公开(公告)日：2016-08-11

申请号：US15019714

申请日：2016-02-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Joon-Sung LEE ,  Suk-Hyeon CHO ,  Yong-Sam LEE

IPC: H05K1/02 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/0271 ,  H05K1/185 ,  H05K3/0029 ,  H05K3/4605 ,  H05K2201/09036 ,  H05K2201/09136 ,  H05K2201/09827 ,  H05K2201/10204

Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a core substrate having a cavity formed therein and a dummy chip inserted in the cavity.

Abstract translation: 提供一种印刷电路板及其制造方法。 印刷电路板包括其中形成有空腔的芯基板和插入空腔中的虚拟芯片。

公开(公告)号：US20160165714A1

公开(公告)日：2016-06-09

申请号：US14603067

申请日：2015-01-22

Applicant: Elite Electronic Material (Zhongshan) Co., Ltd.

Inventor： Ocean CHEN ,  Li-Chih YU ,  Xiangnan LI ,  Xingfa CHEN

IPC: H05K1/02

CPC classification number: H05K3/4602 ,  H05K1/0271 ,  H05K3/4673 ,  H05K2201/09136

Abstract: A multi-layer printed circuit board comprises: a core comprising a core insulation layer and traces formed on two sides of the core insulation layer; a plurality of insulation layers sequentially formed at two sides of the core; and a plurality of trace layers respectively formed between two insulation layers and on the outmost insulation layers; wherein the core insulation layer contains a resin material different from that of the insulation layers, such that the core insulation layer has a warpage characteristic lower than that of the insulation layers.

Abstract translation: 多层印刷电路板包括：芯，其包括芯绝缘层和形成在芯绝缘层的两侧上的迹线; 在芯的两侧依次形成多个绝缘层; 以及分别形成在两个绝缘层之间和最外层绝缘层上的多个迹线层; 其特征在于，所述芯绝缘层含有与所述绝缘层不同的树脂材料，使得所述芯绝缘层的翘曲特性低于所述绝缘层的翘曲特性。