公开(公告)号：JP2578594B2

公开(公告)日：1997-02-05

申请号：JP3687287

申请日：1987-02-18

Applicant: ADVANCED MICRO DEVICES INC

Inventor： RAIONERU EMU DE UETSUKU

IPC: H03K3/353 ,  H03F3/45 ,  H03K3/0233 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24

公开(公告)号：JPH096713A

公开(公告)日：1997-01-10

申请号：JP15016595

申请日：1995-06-16

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BIKUTAA EFU ANDOREEDO ,  KERII EMU HOOTON

IPC: G06F13/16 ,  G06F13/28

Abstract: PURPOSE: To provide a system for optimizing data transfer time between an external master device and a main memory. CONSTITUTION: The system includes an integrated processor provided with a PCT bridge 80 for adjusting data transfer to/from a PCT master 75 and a memory controller 90 for controlling an access to the main memory. When the PCI master 75 can not timely respond, the bridge 80 asserts a MEMWAIT signal to the controller 90 to indicate the necessity of deceleration of data transfer, applies a succeeding memory address to open a proper page in the memory and asserts a suitable row address strobe line to accelerate succeeding data transfer. When the MEMWAIT signal is deasserted, the controller 90 immediately asserts a column address strobe line to drive data. Since the page in the memory is quickly opened, RAS access time and RAS precharging time can be saved.

公开(公告)号：JPH095363A

公开(公告)日：1997-01-10

申请号：JP15438995

申请日：1995-06-21

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SERUJIO AARU RAMAIYAATSU

IPC: G01R19/165

Abstract: PURPOSE: To regulate the hysteresis level independently by regulating a variable state finely using a plurality of comparators. CONSTITUTION: Two comparators 70, 72 and a latch 74 are employed. An input voltage is connected through a signal line 80 with the negative input of a comparator 70 and the positive input of a comparator 74. A reference voltage VREF2 is connected through a signal line 76 with the positive input of the comparator 70 while a reference voltage VREF1 is connected through a signal line 78 with the negative input of the comparator 72. Output of the comparator 72 is connected with the reset input RS of the latch 74. Output and inverted output of the circuit are provided, respectively, from Q and Q/outputs of the latch 74. For example, the output of the latch 74 makes a transition from low to high level when the input voltage signal increases from a level lower than the reference voltage VREF1 to a level higher than the reference voltage VREF1.

公开(公告)号：JPH08330587A

公开(公告)日：1996-12-13

申请号：JP5148096

申请日：1996-03-08

Applicant: ADVANCED MICRO DEVICES INC

Inventor： MOHAMETSUDO ANJIYUUMU ,  KURAUSU EICHI KUUPU ,  MANGU EICHI KIYAU

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure using large tilt angle boron injection for reducing short channel effect and a sub-threshold current on substrate surface and in its vicinity by reducing the shifting or roll-offs of the threshold on the edge of channel. SOLUTION: A semiconductor structure is obtained by injecting boron at a non-vertical angle into the junction part between a channel 14 and a source/ drain 56 and the junction part between a field region 54 and the source/drain 56. By adding boron to a critical region, the threshold adjustment and implantation seeds, which are to be segregated and redistributed caused by the temperature cycle of a process, and a channel-stopping implantation seeds are replenished. By using light-weight boric ions which can be annealed at a low temperature, the disadvantageous redistribution and diffusion caused by high temperature annealing is avoided.

公开(公告)号：JPH08307523A

公开(公告)日：1996-11-22

申请号：JP1519596

申请日：1996-01-31

Applicant: ADVANCED MICRO DEVICES INC

Inventor： HAABAATO EMU KEE CHIEN

IPC: H04M3/02 ,  H04M19/02 ,  H04Q3/42

Abstract: PROBLEM TO BE SOLVED: To provide a ring generator circuit for simultaneously giving high- voltage ring signals to a plurality of ringers in a subscriber's line interface circuit(SLIC). SOLUTION: A ring generator circuit incorporates an adder 530 and a divider circuit which are connected to receive a DC offset signal and an AC reference signal from an SLIC. The adder 530 and divider circuit output a fractionized sum total signal. The signal is supplied to a full-wave rectifier 540 which rectifies the signal so that the signal may always become a positive voltage. The rectified signal is supplied to a switch control circuit 570, a first amplifier 550, and a second amplifier 560. The amplifiers 550 and 560 have the same gain of opposite signs or polarities, and are provided with a signal or a polarity. The outputs of the amplifiers 550 and 560 are sent to a rectifier switch 580 which is contorted by the output of the switch control circuit 570. The output of the control circuit is used for forcibly outputting a ring signal having the same polarity as the sum total signal or the opposite polarity to the switch 580.

公开(公告)号：JPH08304478A

公开(公告)日：1996-11-22

申请号：JP33207495

申请日：1995-12-20

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEFURII JII BUREEMAA ,  KAARIN DORUU KABURAA

IPC: G01R19/165 ,  G05F3/30 ,  G10H1/18 ,  G10H7/02 ,  H03K19/00 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To enhance the dynamic range performance of voice by sensing one of a plurality of power supply voltages to be employed and generating a logic level control signal being used for setting the analog reference voltage levels of A/D and D/A conversion circuits in a voice processing integrated circuit. SOLUTION: A VCCDET block 12 decides whether a voice processing integrated circuit or chip is operating in a 5.0V system or a 3.3V system and sets a digital control signal 5 at logic '1' or '0' level. The control signal 5 has effect on the output signal from a hand cap circuit 22 because the hand cap circuit 22 operates with reference to the output signal from an ARFGEN block 14 and the reference voltage depends on the state of control signal 5. The control signal 5 is fed through a TRIMDS block 18 to a sigma delta A/D conversion circuit 38 and D/A conversion circuit 40 as an analog reference voltage thus producing highest dynamic range and voice performance.

公开(公告)号：JP2552461B2

公开(公告)日：1996-11-13

申请号：JP24018186

申请日：1986-10-08

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JON MAIKERU UINSUN

IPC: H03M1/78 ,  H03M1/00

公开(公告)号：JPH08256053A

公开(公告)日：1996-10-01

申请号：JP4279096

申请日：1996-02-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： OOMU AGURAWARU ,  KAPIRU SHIYANKAA ,  FUARASU ENU MUBARAKU

IPC: G01R31/3185 ,  G06F7/00 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

Abstract: PROBLEM TO BE SOLVED: To improve design flexibility by providing a programmable means which responds to a logic circuit output and generates an output signal, responds to an output enabling signal and connects the output signal to a data node and selects which logic state connects the output signal to the data node. SOLUTION: A programmable AND array 22 uses another combination of logic cells and a product-sum mechanism. A logic signal of a line 24 is given as a combination signal of a product-sum term to OR gates 26, 46 and 74. A common synchronous preset signal and a common asynchronous reset signal are given to an output register part 16 of a PLA device 10, an output micro cell 18 and a register of a buried register part 20. The common preset signal is given as a product term from an output of a programmable AND array 22 to a line 29b. The function of the device 10 is improved by a control signal that is given to a field programmable fuse 32, etc.

公开(公告)号：JPH08255848A

公开(公告)日：1996-10-01

申请号：JP3182996

申请日：1996-02-20

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SETSUDO ENU GUNAIMU ,  EICHI JIMU FURUFUOODO JIYUNIA

IPC: H01L21/8247 ,  H01L21/316 ,  H01L21/336 ,  H01L23/31 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To avoid the charge losing phenomenon by a method wherein a dielectric and dielectric/conductor are formed at a temperature not exceeding a specific value to avoid the formation of the positive-charged atoms in the structure encircling a floating gate. SOLUTION: A pair of dielectrics 70, 72 are formed on the exposed upper side of another pair of electrodes 68, 66. The dielectric layer 70 is formed as an oxide meeting the same requirement as that for the formation of the PECVD layer 66. Accordingly, the SOG layer 68 is held between the PECVD layer 66 and the other PECVD layer 70. In general, when an SOG is formed, considerable amount of hydrogen is produced. These hydrogen are destructed to be shifted as positively charged atoms to a floating conductor 60 operatively programmed at the negative potential. In such a constitution, the hydrogen containing layer such as the SOG layer 68 as well as the next layer to be formed thereon are formed at the temperature not exceeding 380 deg.C for avoiding the production of free hydrogen atoms and the shifting of these atoms to the floating conductors.

公开(公告)号：JPH08255768A

公开(公告)日：1996-10-01

申请号：JP1320396

申请日：1996-01-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： EMU EMU FUARAHAANI ,  SHIYAIAMU GARUGU

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L23/485 ,  H01L29/45 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To increase the coherency of a TiN/Ti/TiSix adhesive layer by forming a Ti layer on a semiconductor Si wafer by the sputter deposition method and by forming specifically controlled nitride and silicide by a rapid heat-treatment method using NH3 . SOLUTION: An Si wafer 10 has a dielectric 12 being formed on a field region 11 and a gate conductor 14, and the gate conductor 14 and a junction region 16 are exposed by a contact hole being formed on the dielectric 12. A thin gate oxide 24 is included between the conductor 14 and a channel 26 of a substrate 18. Then, a Ti layer 3 is deposited on the dielectric 12, the inner wall of the contact hole, the conductor 14, and the region 16. Then, the wafer 10 is subjected to a heat treatment that consists of three annealing cycles or steps and where each cycle is performed at each specific temperature in NH3 . Then, the thickness of TiN barrier and TiSix silicide in regions 5 and 6 is set to a specific thickness, thus increasing coherency.