公开(公告)号：US07520755B2

公开(公告)日：2009-04-21

申请号：US11307425

申请日：2006-02-07

Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu

Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu

IPC: H01R12/00

CPC classification number: H05K3/28 ,  H05K3/3452 ,  H05K2203/013 ,  H05K2203/0557 ,  H05K2203/058 ,  H05K2203/1476

Abstract: A method of forming solder mask, suitable for forming a solder mask on the surface of a wiring board, is provided. The surface of the wiring board includes a first region and a second region, and the surface of the wiring board has a wiring pattern thereon. The method includes forming a first sub solder mask in the first region on the surface of the wiring board by performing a screen-printing or a photolithographic process, and forming a second sub solder mask in the second region on the surface of the wiring board by performing an ink-jet printing process. The method not only improves the precision of the solder mask alignment on the wiring board and its reliability, but also increases the production rate and lowers the manufacturing cost.

Abstract translation: 提供一种形成焊接掩模的方法，该方法适用于在布线板的表面上形成焊接掩模。 布线板的表面包括第一区域和第二区域，并且布线板的表面上具有布线图案。 该方法包括通过丝网印刷或光刻工艺在布线板的表面上的第一区域中形成第一子焊料掩模，并且在布线板的表面上的第二区域中形成第二副焊料掩模 进行喷墨打印处理。 该方法不仅提高了布线板上的焊盘对准的精度及其可靠性，而且提高了生产率，降低了制造成本。

公开(公告)号：US09210815B2

公开(公告)日：2015-12-08

申请号：US13474735

申请日：2012-05-18

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H05K3/36 ,  H05K3/00 ,  H05K3/46 ,  H05K3/10

CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

Abstract: A manufacturing method of an embedded wiring board is provided. The method includes the following steps. First, an insulation layer and a lower wiring layer are provided, wherein the insulation layer includes a polymeric material. Then, the plural catalyst grains are distributed in the polymeric material. A groove and an engraved pattern are formed on the upper surface. A blind via is formed on a bottom surface of the groove to expose the lower pad. An upper wiring layer is formed in the engraved pattern. Some catalyst grains are exposed and activated in the groove, the engraved pattern and the blind via. A first conductive pillar is formed in the groove. Finally, a second conductive pillar is formed in the blind via.

Abstract translation: 提供了一种嵌入式布线板的制造方法。 该方法包括以下步骤。 首先，提供绝缘层和下布线层，其中绝缘层包括聚合材料。 然后，多个催化剂颗粒分布在聚合物材料中。 在上表面上形成有凹槽和雕刻图案。 在槽的底表面上形成盲孔以露出下垫。 上部布线层形成在雕刻图案中。 一些催化剂颗粒在凹槽，雕刻图案和盲孔中暴露和活化。 第一导电柱形成在凹槽中。 最后，在盲通孔中形成第二导电柱。

公开(公告)号：US09084379B2

公开(公告)日：2015-07-14

申请号：US13423578

申请日：2012-03-19

Applicant: Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

Inventor： Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

IPC: H01K3/10 ,  H05K3/00 ,  H05K3/36 ,  H05K1/00 ,  H05K1/14 ,  H05K3/42 ,  H05K3/20

CPC classification number: H05K3/428 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126

Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

Abstract translation: 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。

公开(公告)号：US08436254B2

公开(公告)日：2013-05-07

申请号：US13301812

申请日：2011-11-22

Applicant: Cheng-Po Yu ,  Han-Pei Huang

Inventor： Cheng-Po Yu ,  Han-Pei Huang

IPC: H05K1/00

CPC classification number: H05K1/11 ,  H05K1/0284 ,  H05K1/142 ,  H05K3/185 ,  H05K3/4007 ,  H05K3/4661 ,  H05K2201/0236 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09163 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2203/1327 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T428/24802 ,  Y10T428/24917

Abstract: A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.

Abstract translation: 一种制造电路板结构的方法，包括提供电路板主体，通过封装所述电路板主体的至少一部分来形成具有非板型，立体结构和至少一个刮痕表面的模制的不规则塑料体 并且在所述模制的不规则塑料体上形成第一三维电路图案，从而限定三维电路装置。

公开(公告)号：US08288662B2

公开(公告)日：2012-10-16

申请号：US12718194

申请日：2010-03-05

Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H05K1/11

CPC classification number: H05K3/184 ,  H05K3/0032 ,  H05K3/387 ,  H05K3/421 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2203/107 ,  H05K2203/1173

Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.

Abstract translation: 提供了包括电路板，绝缘层，导电通孔，可镀介电层和导电图案的电路结构。 绝缘层设置在电路板上并覆盖电路板的电路层。 导电通孔穿过绝缘层并连接电路层并从绝缘层的表面突出。 具有沟槽图案的可镀介电层设置在绝缘层的表面上，其中从表面突出的导电通孔的部分位于沟槽图案中。 可镀介电层的材料包括化学镀层材料。 导电图案处于沟槽图案中并且连接导电通孔，其中在导电图案和导电通孔之间存在界面，并从绝缘层的表面突出。

公开(公告)号：US08247705B2

公开(公告)日：2012-08-21

申请号：US12718226

申请日：2010-03-05

Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H05K1/11

CPC classification number: H05K3/387 ,  C23C18/1653 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0145 ,  H05K2201/0154 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

Abstract translation: 电路基板的制造方法包括以下步骤。 在基板的至少一个表面上形成介电层。 在电介质层上形成绝缘层。 去除绝缘层的一部分和电介质层的一部分，以在电介质层和绝缘层中形成至少一个盲孔。 在盲通孔的侧壁和绝缘层的剩余部分上形成化学镀层，其中绝缘层和化学镀层之间的结合强度大于介电层和化学镀层之间的结合强度。 电镀图案化导电层以覆盖化学镀层。

公开(公告)号：US20110155427A1

公开(公告)日：2011-06-30

申请号：US12718226

申请日：2010-03-05

Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H05K1/09 ,  B05D5/12 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/387 ,  C23C18/1653 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0145 ,  H05K2201/0154 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

Abstract translation: 电路基板的制造方法包括以下步骤。 在基板的至少一个表面上形成介电层。 在电介质层上形成绝缘层。 去除绝缘层的一部分和电介质层的一部分，以在电介质层和绝缘层中形成至少一个盲孔。 在盲通孔的侧壁和绝缘层的剩余部分上形成化学镀层，其中绝缘层和化学镀层之间的结合强度大于介电层和化学镀层之间的结合强度。 电镀图案化导电层以覆盖化学镀层。

公开(公告)号：US20110094779A1

公开(公告)日：2011-04-28

申请号：US12718194

申请日：2010-03-05

Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K3/184 ,  H05K3/0032 ,  H05K3/387 ,  H05K3/421 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2203/107 ,  H05K2203/1173

Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.

Abstract translation: 提供了包括电路板，绝缘层，导电通孔，可镀介电层和导电图案的电路结构。 绝缘层设置在电路板上并覆盖电路板的电路层。 导电通孔穿过绝缘层并连接电路层并从绝缘层的表面突出。 具有沟槽图案的可镀介电层设置在绝缘层的表面上，其中从表面突出的导电通孔的部分位于沟槽图案中。 可镀介电层的材料包括化学镀层材料。 导电图案处于沟槽图案中并且连接导电通孔，其中在导电图案和导电通孔之间存在界面，并从绝缘层的表面突出。

公开(公告)号：US20110094778A1

公开(公告)日：2011-04-28

申请号：US12606192

申请日：2009-10-27

Applicant: Cheng-Po Yu ,  Chi-Min Chang ,  Wei-Ming Cheng

Inventor： Cheng-Po Yu ,  Chi-Min Chang ,  Wei-Ming Cheng

IPC: H05K1/00 ,  B23K26/38

CPC classification number: H05K3/185 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0236

Abstract: A method for fabricating a circuit board is provided. A non-conductive material layer is provided on a core substrate, wherein the non-conductive material layer comprises a dielectric material and catalytic particles. A recessed circuit structure is then formed in the non-conductive material layer with a laser beam. Simultaneously, the catalytic particles in the recessed circuit structure are activated with aid of the laser. A buried conductive structure is then formed in the recessed circuit structure by chemical copper deposition methods.

Abstract translation: 提供一种制造电路板的方法。 非导电材料层设置在芯基板上，其中非导电材料层包括电介质材料和催化颗粒。 然后在非导电材料层中用激光束形成凹陷的电路结构。 同时，凹陷电路结构中的催化颗粒借助于激光器被激活。 然后通过化学铜沉积方法在凹陷电路结构中形成掩埋导电结构。

公开(公告)号：US20110023297A1

公开(公告)日：2011-02-03

申请号：US12902518

申请日：2010-10-12

Applicant: Ming-Huan Yang ,  Chung-Wei Wang ,  Chia-Chi Wu ,  Chao-Kai Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Cheng-Po Yu ,  Cheng-Hung Yu

Inventor： Ming-Huan Yang ,  Chung-Wei Wang ,  Chia-Chi Wu ,  Chao-Kai Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Cheng-Po Yu ,  Cheng-Hung Yu

IPC: H05K3/10

CPC classification number: H05K3/182 ,  H05K3/389 ,  H05K3/421 ,  H05K3/422 ,  H05K3/426 ,  H05K3/4661 ,  H05K2203/013 ,  H05K2203/0565 ,  H05K2203/0709 ,  Y10T29/49155

Abstract: A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.

Abstract translation: 一种通过喷墨印刷制造双面或多层印刷电路板（PCB）的方法，其包括提供基板，在所述基板的至少一侧上形成第一自组装膜（SAM），形成非 - 在第一SAM上形成粘合膜，在基底中形成至少一个微孔，在微孔的表面上形成第二SAM，在基底的至少一侧和微孔的表面上形成催化剂颗粒，并形成 基板上的催化剂电路图案。