公开(公告)号：DE602005020218D1

公开(公告)日：2010-05-12

申请号：DE602005020218

申请日：2005-07-28

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： SAHA KAUSHIK ,  SARKAR ABHIK ,  MAITI SRIJIB NARAYAN

IPC: H04N7/50 ,  G06T9/00

Abstract: A macro-block level parallel implementation of a video decoder in parallel processing environment comprising a Variable Length Decoding (VLD) block to decode the encoded Discrete Cosine Transform (DCT) coefficient; a master node which receives said decoded Discrete Cosine Transform (DCT) coefficients; and, plurality of slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at macro-block level.

公开(公告)号：DE602006007778D1

公开(公告)日：2009-08-27

申请号：DE602006007778

申请日：2006-08-29

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： ISANI SONIYA T ,  RADHAKRISHNAN HARIHARASUDHAN K

IPC: G06F13/28 ,  G06F13/42

Abstract: The present invention provides an area efficient system for providing serial access of multiple data buffers to a data retaining and processing device, comprising a signal synchronization and detection means for synchronizing a clock signal and a data signal, a shifting means for receiving and retaining data received from said data bus to thereby generate a status signal indicating the receipt of data; a reference bus address and said data bus. A comparing means is also provided for comparing said reference bus address with the content of said storage means for generating an address matching signal and a control signal generation means for generating control signals to govern the data write signal generation for said shifting means. A sequencing means for reading data from said data retaining and processing device and a direct storage access (DMA) controlling means for generating interrupt signals, access request signals.

公开(公告)号：DE602004009137T2

公开(公告)日：2008-06-19

申请号：DE602004009137

申请日：2004-07-28

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： NANDY TAPAS

IPC: H03K7/06 ,  H03K5/1252 ,  H03K5/13 ,  H03K7/04 ,  H04B15/04 ,  H04L7/00 ,  H04L25/00

Abstract: The present invention provides a digital clock modulator providing a smoothly modulated clock period to reduce emitted Electro-Magnetic Radiation (EMR) comprising a plurality of delay elements (14) connected in series receiving an unmodulated clock signal at the input, connected to a multiplexer (11) receiving inputs from unequally spaced selected taps provided between the delay elements. A control block (12) supplies the selection-inputs to said multiplexer (11), and receives a clock signal from said series of delay elements. Further, a predetermined delay element (13) is connected between the clock terminal of the said control block (12) and the last element U(n) of said series of delay elements for enabling glitch free operation by ensuring that the entire delay chain and related signal paths are in the same stable state before the control to the multiplexer changes.

公开(公告)号：DE602005003309D1

公开(公告)日：2007-12-27

申请号：DE602005003309

申请日：2005-12-02

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： JAISINGHANI POOJA ,  NANDY TAPAS

IPC: G06F1/28 ,  G01R19/165 ,  G06F1/26 ,  G11C16/30

公开(公告)号：DE602005002774D1

公开(公告)日：2007-11-22

申请号：DE602005002774

申请日：2005-04-06

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： BAHL SWAPNIL ,  SINGH BALWANT

IPC: G06F5/06 ,  G06F5/10 ,  G11C7/10

Abstract: An improved on-chip storage memory for storing variable data bits comprising an on-chip storage memory system for storing variable data bits comprising a memory for storing data bits; a wrapper for converting said memory into a first-in first-out (FIFO) memory; and a controller for performing operations on said memory.

公开(公告)号：DE60218928D1

公开(公告)日：2007-05-03

申请号：DE60218928

申请日：2002-04-18

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： CHELLADURAI PAUL SATHYA ,  AHMED ARSHAD ,  NANDY SOUMITRA KUMAR

IPC: H04N7/26 ,  H04N7/50

Abstract: The present invention provides a system, method and computer program product for efficient low power motion estimation of a digital video image wherein processing requirements are reduced, the reduction being dependent on the content being processed. The method performs motion estimation of a current video image using a search window of previous video image. The method comprises as a first step the formation of the mean pyramids of the reference macroblock and the search area. This is followed by full search at the lowest resolution. The number of CMVs propagated to lower levels is dependent on the QADE of the current macroblock and the maximum distortion band obtained during training for that QADE value at that particular level. The process of training over a sequence is triggered at the beginning of every sequence. This training technique is required to determine the value of the maximum distortion band for all QADEs of the macroblocks, occurring over the training frames.

公开(公告)号：FR2961978B1

公开(公告)日：2013-11-22

申请号：FR1055092

申请日：2010-06-25

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS PVT LTD

Inventor： SINGH PRATAP NARAYAN ,  LE TUAL STEPHANE

IPC: H03K19/00

公开(公告)号：ITTO20111080A1

公开(公告)日：2013-05-24

申请号：ITTO20111080

申请日：2011-11-23

Applicant: ST MICROELECTRONICS PVT LTD ,  ST MICROELECTRONICS SRL

Inventor： KUMAR ASHISH ,  RIMONDI DANILO ,  SELVA CAROLINA

公开(公告)号：FR2961978A1

公开(公告)日：2011-12-30

申请号：FR1055092

申请日：2010-06-25

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS PVT LTD

Inventor： SINGH PRATAP NARAYAN ,  LE TUAL STEPHANE

IPC: H03K19/00

Abstract: L'invention concerne un circuit à source commune comprenant deux branches en parallèle entre une borne (21) d'application d'un potentiel (Vdd) et une source de courant (29), chaque branche comportant : une association en série d'une résistance (22 , 22 ) et d'un transistor (24 , 24 ) dont le point milieu définit une borne de sortie (OUTM, OUTP) de la branche ; un premier interrupteur (12 , 12 ) reliant une borne d'entrée (INP, INM) de la branche à une borne de commande du transistor (24 , 24 ) ; et un étage commandable d'amplification d'une information représentant le niveau présent sur la borne de sortie de la branche opposée.

公开(公告)号：DE602005019841D1

公开(公告)日：2010-04-22

申请号：DE602005019841

申请日：2005-08-26

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： CHATTERJEE KALLOL ,  JAIN DEEPENDRA

IPC: H03K23/66 ,  H03K23/58

Abstract: A programmable high-speed frequency divider, in which stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified to reduce the area and circuit complexity. A start-up circuitry has been introduced within the said frequency-divider to ensure that the frequency-divider will never go into false state.