公开(公告)号：KR1020120075037A

公开(公告)日：2012-07-06

申请号：KR1020100137056

申请日：2010-12-28

Applicant: 삼성전자주식회사

Inventor： 김준성 ,  신혜수 ,  김미연 ,  김영수

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/0273 ,  H01L21/28282 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/76877

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to form a semiconductor device with multilayer step profile through a photolithography and an etching process. CONSTITUTION: A stack structure is formed by alternately laminating a plurality of insulating films(20) and conductive films(30) on a substrate(10). The insulating film includes a first insulating film(21), a second insulating film(22), and a third insulating film(23). The conductive film includes a first conductive film(31), a second conductive film(32), and a third conductive film(33). A first photoresist pattern is formed on the stack structure. A second photoresist pattern(43) is formed by thermally processing the first photoresist pattern.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过光刻和蚀刻工艺形成具有多层台阶轮廓的半导体器件。 构成：通过在基板（10）上交替层叠多个绝缘膜（20）和导电膜（30）而形成堆叠结构。 绝缘膜包括第一绝缘膜（21），第二绝缘膜（22）和第三绝缘膜（23）。 导电膜包括第一导电膜（31），第二导电膜（32）和第三导电膜（33）。 在堆叠结构上形成第一光致抗蚀剂图案。 通过热处理第一光致抗蚀剂图案形成第二光致抗蚀剂图案（43）。

公开(公告)号：KR1020120070093A

公开(公告)日：2012-06-29

申请号：KR1020100131508

申请日：2010-12-21

Applicant: 삼성전자주식회사

Inventor： 변학균 ,  최대영 ,  김미연

IPC: H01L23/31 ,  H01L23/48 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17179 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PURPOSE: A semiconductor package and a package on package including the same are provided to improve the reliability of a package on package by preventing a short phenomenon between adjacent connection conductors. CONSTITUTION: A semiconductor chip(140) is attached to an upper side of a substrate. A plurality of connection conductors(135) is arranged on the upper side of the substrate. A molding material(150) fills in the plurality of connection conductors and a semiconductor chip while being formed on the substrate. A plurality of connection via holes(152) respectively exposes the plurality of connection conductors passing through the molding material. A plane distance from a first connection conductor exposed by a first connection via hole to an entrance of the first connection via hole is not uniform to the first connection via hole from the plurality of connection via holes.

Abstract translation: 目的：提供一种半导体封装和包括其的封装，以通过防止相邻连接导体之间的短暂现象来提高封装上封装的可靠性。 构成：半导体芯片（140）附着到基板的上侧。 多个连接导体（135）设置在基板的上侧。 成型材料（150）在形成在基板上的同时填充多个连接导体和半导体芯片。 多个连接通孔（152）分别暴露穿过成型材料的多个连接导体。 从第一连接通孔露出的第一连接导体到第一连接通孔的入口的平面距离对于来自多个连接通孔的第一连接通孔是不均匀的。

公开(公告)号：KR1020110099555A

公开(公告)日：2011-09-08

申请号：KR1020100018644

申请日：2010-03-02

Applicant: 삼성전자주식회사

Inventor： 임충빈 ,  목승곤 ,  박진우 ,  최대영 ,  김미연

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

Abstract: 적층형 반도체 패키지 및 그 제조방법을 제공한다. 제 1 인쇄 회로 기판과 상기 제 1 인쇄 회로 기판에 실장되는 제 1 반도체 소자를 구비하는 제 1 반도체 패키지와, 상기 제 1 반도체 패키지에 적층되고, 제 2 인쇄 회로 기판과 상기 제 2 인쇄 회로 기판에 실장되는 제 2 반도체 소자를 구비하는 제 2 반도체 패키지를 제공한다. 상기 제 1 반도체 소자를 관통하여 상기 제 2 반도체 패키지와 상기 제 1 인쇄 회로 기판을 전기적으로 연결하는 적어도 하나의 제 1 관통전극을 제공한다.

Abstract translation: 半导体封装包括第一半导体封装，包括第一印刷电路板和安装在第一印刷电路板上的第一半导体器件，以及堆叠在第一半导体封装上的第二半导体封装，并且包括第二印刷电路板和第二半导体 装置安装在第二印刷电路板上。 半导体封装包括至少一个第一通孔，其通过第一半导体器件将第二半导体封装电连接到第一印刷电路板。

公开(公告)号：KR1020100129577A

公开(公告)日：2010-12-09

申请号：KR1020090048214

申请日：2009-06-01

Applicant: 삼성전자주식회사

Inventor： 임충빈 ,  김동한 ,  목승곤 ,  박진우 ,  이파란 ,  김미연

IPC: H01L23/12 ,  H01L23/28

CPC classification number: H01L23/04 ,  H01L23/3128 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/0401

Abstract: PURPOSE: A method for forming a semiconductor device package is provided to form a package structure with high reliability by controlling the shape of a via hole. CONSTITUTION: The lower side of a molding cap(120) is formed with a recess structure(123) corresponding to a first package. A first package is formed by providing a first chip to a first substrate. The first substrate is electrically connected to the first chip with a bonding bump or bonding wire. A first pad is formed on the upper side of the first substrate for electrical connection.

Abstract translation: 目的：提供一种形成半导体器件封装的方法，通过控制通孔的形状来形成具有高可靠性的封装结构。 构成：成形盖（120）的下侧形成有与第一包装对应的凹部结构（123）。 通过向第一基板提供第一芯片形成第一封装。 第一基板通过接合凸块或接合线与第一芯片电连接。 第一衬垫形成在第一衬底的上侧，用于电连接。

公开(公告)号：KR1020090009056A

公开(公告)日：2009-01-22

申请号：KR1020070072493

申请日：2007-07-19

Applicant: 삼성전자주식회사

Inventor： 김미연 ,  유지용

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/265 ,  H01L21/67294 ,  H01L2223/54433

Abstract: The semiconductor substrate and recognition apparatus are provided to suppress the generation of particle in the semiconductor substrate and to form a label on the surface of the semiconductor substrate without forming the physical hole. The semiconductor substrate comprises the first area and the second part. The first area is comprised of the labeling region among the semiconductor substrate. The second part is comprised of the part except for the labeling region. The optical characteristic of the first area is different from the optical characteristic of the second part to distinct the first area and the second part. The first area of the semiconductor substrate is automatically acknowledged with the semiconductor substrate recognizing apparatus.

Abstract translation: 提供半导体衬底和识别装置以抑制半导体衬底中的颗粒的产生并且在不形成物理孔的情况下在半导体衬底的表面上形成标签。 半导体衬底包括第一区域和第二部分。 第一区域由半导体衬底中的标记区域组成。 第二部分由除标签区域外的部分组成。 第一区域的光学特性与第二部分的光学特性不同，以区分第一区域和第二部分。 半导体衬底识别装置自动确认半导体衬底的第一区域。

公开(公告)号：KR1020060129772A

公开(公告)日：2006-12-18

申请号：KR1020050050419

申请日：2005-06-13

Applicant: 삼성전자주식회사

Inventor： 배용국 ,  김미연 ,  고용선 ,  윤경선

IPC: H01L21/027

CPC classification number: G03F7/70733 ,  G03F7/707 ,  G03F7/70916

Abstract: A reticle arm and an exposure apparatus having the same are provided to reduce a time for preparing reticle by loading and arranging a plurality of reticles on a plurality of reticle arms. A reticle arm includes a first connection part(1410), a supporting part(1420), and a second connection part(1430). The first connection part is connected with a rail. The supporting part is connected with the first connection part. The second connection part is projected from the supporting part and is fixed to a lateral face of the reticle. The second connection part and the supporting part are integrated. The second connection part is inserted into a concave part which is formed on the lateral face of the reticle.

Abstract translation: 提供了一种掩模版臂和具有该掩模版臂的曝光设备，以通过在多个掩模版臂上装载和布置多个掩模版来减少准备掩模版的时间。 标线臂包括第一连接部分（1410），支撑部分（1420）和第二连接部分（1430）。 第一连接部分与导轨连接。 支撑部与第一连接部连接。 第二连接部从支撑部突出并固定在标线的侧面。 第二连接部和支撑部被集成。 第二连接部被插入形成在标线片的侧面上的凹部中。