公开(公告)号：KR100435261B1

公开(公告)日：2004-06-11

申请号：KR1020020046499

申请日：2002-08-07

Applicant: 삼성전자주식회사

Inventor： 권철순 ,  유재민 ,  김진우 ,  박재현 ,  김용희 ,  이돈우 ,  김대근 ,  박상욱 ,  김주찬 ,  김국민 ,  조민수 ,  류의열

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectric film and the first conductive film exposed by the removal of the second dielectric film using the fourth dielectric film as an etch mask, and forming a second gate dielectric film and a word line.

Abstract translation: 制造分栅快闪存储器件的方法包括以下步骤：（a）提供导电类型与第一结区的导电类型相反的半导体衬底; （b）在衬底的整个上表面上顺序地形成第一电介质膜，第一导电膜，第二电介质膜和第三电介质膜; （c）将第三电介质膜蚀刻一定的厚度以暴露第二电介质膜; （d）去除暴露的第二介电膜，并去除剩余的第三介电膜; （e）将所述第一导电膜和所述第二电介质膜蚀刻预定的厚度，以部分暴露所述第一导电线和所述第一导电膜; （f）在暴露的第一导线和第一导电膜的一部分上形成第四介电膜; （g）除去剩余的第二电介质膜，并暴露设置在其下部的第一导电膜; （h）使用第四电介质膜作为蚀刻掩模，蚀刻通过去除第二电介质膜而暴露的第一电介质膜和第一导电膜，以及形成第二栅极电介质膜和字线。