中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

302 records (took 0.038 seconds)

    반도체 소자 및 그 제조 방법
    21.
    发明公开
    반도체 소자 및 그 제조 방법 有权
    半导体及其制造方法

    公开(公告)号：KR1020110129256A

    公开(公告)日：2011-12-01

    申请号：KR1020100048795

    申请日：2010-05-25

    Applicant: 삼성전자주식회사

    Inventor： 황성민 ,  김경훈 ,  김한수 ,  손병근 ,  심재주 ,  장재훈 ,  조원석 ,  조후성

    IPC: H01L27/10 ,  H01L21/70 ,  H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/0688 ,  H01L21/76816 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/11551 ,  H01L27/11578

    Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to stably supply voltage on a substrate through a pickup area which is electrically connected to the substrate, thereby making the semiconductor device with excellent reliability. CONSTITUTION: A substrate(100) is doped with a first conductive type dopant. A plurality of laminate structures is extended side by side to a first direction on the substrate. Each laminate structure comprises gate electrodes(157L,157,157U) which is laminated by being separated from each other on the substrate. A plurality of laminate structures comprises a pair of the laminate structures which is perpendicular to the first direction and separated with a first interval to a second direction. A pickup region(176) is extended to the first direction within the substrate between the pair of the laminated structures and doped with the first conductive type dopant.

    Abstract translation: 目的：提供半导体器件及其制造方法，通过与基板电连接的拾取区域稳定地在基板上提供电压，从而使半导体器件具有良好的可靠性。 构成：衬底（100）掺杂有第一导电型掺杂剂。 多个层压结构在基板上沿第一方向并排延伸。 每个层压结构包括通过在基板上彼此分离而层压的栅电极（157L，157,157U）。 多个层叠结构包括一对垂直于第一方向并且以第一间隔分离成第二方向的层压结构。 拾取区域（176）在衬底之间的第一方向延伸到一对层压结构之间并掺杂有第一导电型掺杂剂。

    반도체 소자 및 그 제조 방법
    22.
    发明公开
    반도체 소자 및 그 제조 방법 有权
    半导体器件及其制造方法

    公开(公告)号：KR1020110126999A

    公开(公告)日：2011-11-24

    申请号：KR1020100046593

    申请日：2010-05-18

    Applicant: 삼성전자주식회사

    Inventor： 황성민 ,  김한수 ,  조원석 ,  장재훈 ,  심재주

    IPC: H01L27/115 ,  H01L27/02

    CPC classification number: H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    Abstract: PURPOSE: A semiconductor device and a method of fabricating the same are provided to minimize an over etching due to the height difference between contact holes by forming a reserved contact hole through a barrier rip. CONSTITUTION: In a semiconductor device and a method of fabricating the same, a substrate(100) comprises a first area(10) and a second area(20). A pattern structure including each pattern(108) is arranged on the substrate within the first area. A conductive pattern(CP) is arranged on the substrate within the second area. The conductive patterns includes a connection unit connecting a plurality of gate electrodes and one end of a gate electrode. A semiconductor pillar(130) comprises a semiconductor(131), a filling insulating material(132), and a drain(133).

    Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过形成通过阻挡层的保留接触孔来最小化由于接触孔之间的高度差引起的过度蚀刻。 构成：在半导体器件及其制造方法中，衬底（100）包括第一区域（10）和第二区域（20）。 包括每个图案（108）的图案结构布置在第一区域内的基板上。 导电图案（CP）布置在第二区域内的基板上。 导电图案包括连接多个栅电极和栅电极的一端的连接单元。 半导体柱（130）包括半导体（131），填充绝缘材料（132）和漏极（133）。

    3차원 반도체 기억 소자
    24.
    发明公开
    3차원 반도체 기억 소자 有权
    三维半导体存储器件

    公开(公告)号：KR1020110054361A

    公开(公告)日：2011-05-25

    申请号：KR1020090110975

    申请日：2009-11-17

    Applicant: 삼성전자주식회사

    Inventor： 심선일 ,  허성회 ,  김한수 ,  장재훈 ,  조후성

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L21/02365 ,  H01L21/02697 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7841

    Abstract: PURPOSE: A three dimensional semiconductor memory device is provided to operate at high speed and improve reliability by decreasing resistance between sub gates. CONSTITUTION: A substrate has a pair of sub cell regions and a cell array region including a strapping region. A plurality of sub gates(135a,135au,135b,135bu) are successively laminated in each sub cell region. Each sub gate has an extension unit which is extended in the strapping region. A vertical type channel pattern successively passes through the sub gates laminated in each sub cell region. The wirings are electrically connected to the extension units of the sub gates. Each wire is arranged in the pair of sub cell regions and is electrically connected to the extension units of the pair of sub gates on the same level.

    Abstract translation: 目的：提供三维半导体存储器件，通过降低子门之间的电阻，高速运行并提高可靠性。 构成：衬底具有一对子电池区域和包括带状区域的电池阵列区域。 多个子门（135a，135au，135b，135bu）依次层叠在每个子单元区域中。 每个子门具有在捆扎区域中延伸的延伸单元。 垂直型通道图案依次通过层叠在每个子单元区域中的子门。 配线电连接到子门的延伸单元。 每根导线布置在一对子单元区域中，并且与同一电平上的一对子门的延伸单元电连接。

    3차원 반도체 메모리 장치 및 그 제조 방법
    25.
    发明公开
    3차원 반도체 메모리 장치 및 그 제조 방법 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：KR1020110029403A

    公开(公告)日：2011-03-23

    申请号：KR1020090087063

    申请日：2009-09-15

    Applicant: 삼성전자주식회사

    Inventor： 심선일 ,  장재훈 ,  김한수 ,  황성민 ,  조원석 ,  임진수

    IPC: H01L27/10 ,  H01L21/82

    CPC classification number: H01L29/7926 ,  H01L27/11556 ,  H01L27/11582

    Abstract: PURPOSE: A three dimensional semiconductor memory device and a manufacturing method thereof are provided to restrain the non-uniformity in the electrical characteristic between the memory cells by forming the lower and upper semiconductor patterns using the same material without discontinuous boundary. CONSTITUTION: A lower part thin film structure(100) is formed on a substrate(10). The lower part thin film structure comprises a plurality of bottom insulating layers(121~127) and a plurality of lower part sacrificing layers(131~136). A lower penetration hole(140) passes through the lower part thin film structure. A bottom semiconductor pattern(150) fills the lower penetration holes.

    Abstract translation: 目的：提供三维半导体存储器件及其制造方法，以通过使用相同材料形成下部和上部半导体图案来不间断地限制存储单元之间的电气特性的不均匀性。 构成：在基板（10）上形成下部薄膜结构（100）。 下部薄膜结构包括多个底部绝缘层（121〜127）和多个下部牺牲层（131〜136）。 下穿孔（140）穿过下部薄膜结构。 底部半导体图案（150）填充下部穿透孔。

    3차원 반도체 메모리 장치 및 그 제조 방법
    26.
    发明公开
    3차원 반도체 메모리 장치 및 그 제조 방법 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：KR1020110021444A

    公开(公告)日：2011-03-04

    申请号：KR1020090079243

    申请日：2009-08-26

    Applicant: 삼성전자주식회사

    Inventor： 손병근 ,  김한수 ,  안영수 ,  김민구 ,  김진호 ,  최재형 ,  최석헌

    IPC: H01L27/115

    CPC classification number: H01L27/11575 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L27/0688 ,  H01L21/76897 ,  H01L27/2463 ,  H01L2924/00

    Abstract: PURPOSE: A 3d semiconductor memory apparatus and a manufacturing method thereof are provided to obtain the forming margin of a contact plugs or wirings directly connected to the contact extensions by arranging the contact extensions and the even conductive patterns on the different contact areas. CONSTITUTION: A substrate(10) comprises a cell array region(CAR) and contact areas(CR1, CR2). An extrusion oxide(11) is arranged on the contact area of the substrate. A plurality of conductive patterns(GL1~GL6) is deposited with an interval on the substrate. The conductive pattern comprises a wire portion(IC) which is parallel to the substrate and a contact extension part(CT) being tilted to the substrate.

    Abstract translation: 目的：提供3d半导体存储装置及其制造方法，以通过将接触延伸部和偶数导电图案布置在不同的接触区域上来获得直接连接到接触延伸部的接触插塞或布线的成形边缘。 构成：衬底（10）包括电池阵列区（CAR）和接触区（CR1，CR2）。 挤出氧化物（11）设置在基板的接触区域上。 多个导电图案（GL1〜GL6）在衬底上以间隔沉积。 导电图案包括平行于基板的导线部分（IC）和向基板倾斜的接触延伸部分（CT）。

    비휘발성 메모리 장치
    28.
    发明公开
    비휘발성 메모리 장치 有权
    非易失性存储器件

    公开(公告)号：KR1020100112862A

    公开(公告)日：2010-10-20

    申请号：KR1020090031368

    申请日：2009-04-10

    Applicant: 삼성전자주식회사

    Inventor： 정재훈 ,  김한수 ,  장재훈 ,  조후성 ,  김경훈

    IPC: H01L27/115 ,  G11C16/02

    CPC classification number: H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/02 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/0688

    Abstract: PURPOSE: A nonvolatile memory device is provided to form a word line without disconnection by forming cell arrays with a separated structure to provide a space for strapping a common source region or/and well region. CONSTITUTION: A first cell array(130a) and a second cell array(130b) are arranged on a semiconductor substrate. A common source region is formed on the semiconductor substrate under semiconductor patterns. A first impurity region electrically connects the common source regions. A first contact hole expose the part of the first impurity region between the separated cell arrays. Common source lines(170S) and well lines(170W) are formed on contact plugs.

    Abstract translation: 目的：提供非易失性存储器件，以通过形成具有分离结构的单元阵列来形成字线而不断开以提供用于捆扎公共源区域或/和阱区域的空间。 构成：第一电池阵列（130a）和第二电池阵列（130b）布置在半导体衬底上。 在半导体图案下的半导体衬底上形成公共源极区域。 第一杂质区域电连接共同的源极区域。 第一接触孔暴露分离的电池阵列之间的第一杂质区域的一部分。 公共源极线（170S）和阱线（170W）形成在接触插塞上。

    반도체 장치 및 그 형성 방법
    29.
    发明公开
    반도체 장치 및 그 형성 방법 有权
    半导体器件及其形成方法

    公开(公告)号：KR1020100109745A

    公开(公告)日：2010-10-11

    申请号：KR1020090028159

    申请日：2009-04-01

    Applicant: 삼성전자주식회사

    Inventor： 심재주 ,  김한수 ,  조원석 ,  심선일 ,  임주영

    IPC: H01L21/82

    Abstract: PURPOSE: The semiconductor device and formation method the semiconductor device with a superior quality the peripheral circuit is formed on the spark region and formation method can be offered. The opening having the high level difference offers the removed semiconductor device and a method of formation thereof and the quality excellent. CONSTITUTION: The semiconductor device and formation method comprises the recess region(106) and the spark region(108) including the floor side and side are formed on the semiconductor substrate. Plateau on the floor side of the recess region and the sidewall part expanded from plateau as the side are included.

    Abstract translation: 目的：半导体器件和形成方法是具有优异质量的半导体器件，外围电路形成在火花区域上，并且可以提供形成方法。 具有高电平差的开口提供了去除的半导体器件及其形成方法，并且质量优异。 构成：半导体器件和形成方法包括凹部区域（106），并且包括地板侧和侧面的火花区域（108）形成在半导体衬底上。 包括在凹部区域的地板侧的高原以及从侧面扩张的侧壁部分。

Patent Agency Ranking