公开(公告)号：KR1020040070617A

公开(公告)日：2004-08-11

申请号：KR1020030006791

申请日：2003-02-04

Applicant: 삼성전자주식회사

Inventor： 최재형 ,  임한진 ,  정정희 ,  이윤정 ,  유차영 ,  여재현

IPC: H01L27/108

Abstract: PURPOSE: A semiconductor memory device and a fabricating method thereof are provided to enhance a dielectric characteristic and a leakage current characteristic of a dielectric layer by forming a dielectric layer as a hafnium layer. CONSTITUTION: A bottom electrode(110) is formed on a semiconductor substrate(100). A crystalline seed layer(120a) is formed on the bottom electrode. A main dielectric layer(125a) is formed on the crystalline seed layer. The main dielectric layer has the different physical property from the crystalline seed layer. A top electrode(130) is formed on the main dielectric layer. The main dielectric layer includes one or more of a grain boundary and a continuous grain boundary of the crystalline seed layer.

Abstract translation: 目的：提供半导体存储器件及其制造方法，通过形成作为铪层的电介质层来提高电介质层的介电特性和漏电流特性。 构成：在半导体衬底（100）上形成底部电极（110）。 在底部电极上形成结晶种子层（120a）。 在结晶种子层上形成主介电层（125a）。 主介电层与晶种层具有不同的物理性质。 顶电极（130）形成在主电介质层上。 主介电层包括结晶种子层的晶界和连续晶界中的一种或多种。

公开(公告)号：KR1020040022648A

公开(公告)日：2004-03-16

申请号：KR1020020054260

申请日：2002-09-09

Applicant: 삼성전자주식회사

Inventor： 정숙진 ,  유차영 ,  김완돈

IPC: H01L27/108

Abstract: PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to simplify a fabricating process and reduce fabricating cost by removing the step between the cell array region and the peripheral region without using a planarization process. CONSTITUTION: A molding insulation layer is formed to cover conductive plugs(104) on a semiconductor substrate(100). The molding insulation layer is partially removed to form a plurality of openings for exposing the conductive plugs in the cell array region. A plurality of storage nodes(118) whose nodes are mutually separated are formed, contacting the conductive plugs in the openings. A lift-off stop layer(120) is formed on the molding insulation layer and the storage node in the cell array region and the molding insulation layer in the peripheral region. While the lift-off stop layer in the peripheral region is left, only the lift-off stop layer in the cell array region is selectively removed to expose the molding insulation layer in the cell array region. The exposed molding insulation layer in the cell array region is eliminated to expose the outer wall of the storage node. The lift-off insulation layer that remains on the inner wall of the storage node in the cell array region and on the molding insulation layer in the peripheral region is removed to expose the inner wall of the storage node. A dielectric layer and a plate electrode are sequentially formed on the storage node whose inner and outer wall is exposed.

Abstract translation: 目的：提供一种用于制造半导体器件的电容器的方法，以简化制造工艺并且通过在不使用平坦化工艺的情况下去除电池阵列区域和周边区域之间的步骤来降低制造成本。 构成：形成模制绝缘层以覆盖半导体衬底（100）上的导电插塞（104）。 部分去除模制绝缘层以形成用于暴露电池阵列区域中的导电插塞的多个开口。 其节点相互分离的多个存储节点（118）形成为与开口中的导电插头接触。 在模制绝缘层和电池阵列区域中的存储节点和外围区域中的模制绝缘层上形成剥离阻挡层（120）。 当外围区域中的剥离停止层留下时，仅选择性地除去电池阵列区域中的剥离停止层以露出电池阵列区域中的模塑绝缘层。 消除电池阵列区域中暴露的成型绝缘层，露出存储节点的外壁。 保留在电池阵列区域中的存储节点的内壁上和外围区域中的成型绝缘层上的剥离绝缘层被去除以暴露存储节点的内壁。 介电层和平板电极顺序地形成在其内壁和外壁暴露的存储节点上。

公开(公告)号：KR100421044B1

公开(公告)日：2004-03-04

申请号：KR1020010038160

申请日：2001-06-29

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  유차영 ,  박영욱

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor memory device is provided to prevent a leakage current on an interface between a dielectric layer and the second electrode layer so that the thickness of an equivalent oxide layer of the dielectric layer is reduced, by using polysilicon to form the first electrode of a lower electrode and by using a Ru layer to form the second electrode layer of an upper electrode wherein the Ru layer has a relatively high electrical barrier. CONSTITUTION: A silicon nitride layer(40) is formed on the lower electrode. A metal oxide dielectric layer(50) is formed on the silicon nitride layer opposite to the lower electrode. The dielectric layer is formed on the lower electrode. The upper electrode composed of the Ru layer is formed on the dielectric layer.

Abstract translation: 目的：提供一种用于制造半导体存储器件的电容器的方法，以防止介电层和第二电极层之间的界面上的泄漏电流，从而通过使用介电层的等效氧化物层的厚度减小 形成下电极的第一电极并通过使用Ru层来形成上电极的第二电极层，其中Ru层具有相对高的电阻挡。 构成：氮化硅层（40）形成在下电极上。 金属氧化物介电层（50）形成在与下电极相对的氮化硅层上。 介电层形成在下电极上。 在电介质层上形成由Ru层构成的上部电极。

公开(公告)号：KR1020030024212A

公开(公告)日：2003-03-26

申请号：KR1020010057263

申请日：2001-09-17

Applicant: 삼성전자주식회사

Inventor： 김완돈 ,  유차영 ,  황두섭 ,  주재현 ,  정은애 ,  정용국

IPC: H01L27/04

CPC classification number: H01L28/55 ,  H01L28/60 ,  H01L28/91

Abstract: PURPOSE: A method of fabricating a capacitor of a semiconductor memory device for controlling a thermal budget is provided to prevent leakage current by performing a preheating process for a bottom electrode in a thermal process for crystallizing a dielectric layer. CONSTITUTION: A bottom electrode(22a) is formed on an upper surface of a semiconductor substrate(10). A thermal process for the bottom electrode(22a) is performed by using the first thermal budget. A dielectric layer(32) is formed on the bottom electrode(22a). The dielectric layer(22a) is crystallized by using the second thermal budget. The bottom electrode(22a) is formed with noble metal, conductive noble metal oxide, and conductive metal oxide. The bottom electrode(22a) is formed with Pt, Ru, Ir, PtO, RuO2, IrO2, SrRuO3, BaSrRuO3, or LaScCo.

Abstract translation: 目的：提供一种制造用于控制热量预算的半导体存储器件的电容器的方法，以通过在用于结晶电介质层的热处理中对底部电极进行预热处理来防止漏电流。 构成：在半导体衬底（10）的上表面上形成底电极（22a）。 通过使用第一热预算执行底部电极（22a）的热处理。 在底部电极（22a）上形成介电层（32）。 通过使用第二热预算使电介质层（22a）结晶。 底部电极（22a）由贵金属，导电贵金属氧化物和导电金属氧化物形成。 底部电极（22a）由Pt，Ru，Ir，PtO，RuO2，IrO2，SrRuO3，BaSrRuO3或LaScCo形成。

公开(公告)号：KR1020030010851A

公开(公告)日：2003-02-06

申请号：KR1020010045486

申请日：2001-07-27

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  박순연 ,  유차영

IPC: H01L27/04

CPC classification number: H01L28/60 ,  C23C16/0281 ,  C23C16/18 ,  H01L21/28556 ,  H01L28/55

Abstract: PURPOSE: A method for fabricating a semiconductor device is provided to prevent degradation of an interfacial characteristic between a ruthenium layer and an underlying layer by preventing etchant from penetrating the layer positioned under the ruthenium layer when a silicon oxide layer in contact with the ruthenium layer is eliminated. CONSTITUTION: A semiconductor fabricating apparatus is connected to a ruthenium source supply and an oxygen gas supply source. An insulation layer(42) having an opening(46) of a vertical profile is formed on a wafer introduced into the semiconductor fabricating apparatus. A sputtering process is performed at the first pressure to form a ruthenium seeding layer(43) on the sidewall and inner wall of the opening of the insulation layer. A chemical vapor deposition(CVD) process is performed at the second pressure higher than the first pressure and at the first flow rate of oxygen gas so that a ruthenium seeding compensation layer is formed on the ruthenium seeding layer. A CVD process is performed at the third pressure higher than the first pressure and at the second flow rate of oxygen gas so that a ruthenium main layer is formed on the ruthenium seeding compensation layer.

Abstract translation: 目的：提供一种制造半导体器件的方法，以防止当与钌层接触的氧化硅层为钌层时，通过防止蚀刻剂穿过位于钌层下方的层而降低钌层与下层之间的界面特性 淘汰。 构成：半导体制造装置连接到钌源电源和氧气供应源。 在引入半导体制造装置的晶片上形成具有垂直剖面的开口（46）的绝缘层（42）。 在第一压力下进行溅射工艺，以在绝缘层的开口的侧壁和内壁上形成钌接种层（43）。 在高于第一压力和氧气的第一流量的第二压力下进行化学气相沉积（CVD）工艺，从而在钌接种层上形成钌接种补偿层。 在比第一压力高的第三压力和氧气的第二流量下进行CVD处理，使得在钌籽晶补偿层上形成钌主层。

公开(公告)号：KR1020020066669A

公开(公告)日：2002-08-21

申请号：KR1020010006984

申请日：2001-02-13

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  유차영

IPC: H01L27/108

Abstract: PURPOSE: A formation method of storage electrodes of semiconductor devices is provided to protect an interlayer dielectric and to improve a stability by additionally forming an insulating layer on a lower portion of the storage electrode. CONSTITUTION: Bit lines(118) respectively capped with bit line protection layer(120) are formed on a semiconductor substrate formed with the first insulating layer(116). Then, the second insulating layer(122a) and the third insulating layer(124a) are sequentially formed on the resultant structure. A storage contact hole is formed by selectively etching the third, second and first insulating layers(124a,122a,116). Then, a conductive plug is formed by filling the storage contact hole with a conductive material. An additional fourth insulating layer(132) is formed on the entire surface of the resultant structure. After selectively etching the fourth insulating layer(132), a platinum group metal is deposited.

Abstract translation: 目的：提供半导体器件的存储电极的形成方法以保护层间电介质并通过在存储电极的下部另外形成绝缘层来提高稳定性。 构成：分别用位线保护层（120）覆盖的位线（118）形成在形成有第一绝缘层（116）的半导体衬底上。 然后，在所得到的结构上依次形成第二绝缘层（122a）和第三绝缘层（124a）。 通过选择性地蚀刻第三，第二和第一绝缘层（124a，122a，116）形成存储接触孔。 然后，通过用导电材料填充存储接触孔来形成导电插塞。 在所得结构的整个表面上形成另外的第四绝缘层（132）。 在选择性蚀刻第四绝缘层（132）之后，沉积铂族金属。

公开(公告)号：KR1020020049389A

公开(公告)日：2002-06-26

申请号：KR1020000078547

申请日：2000-12-19

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  이윤정 ,  박순연 ,  유차영 ,  황두섭 ,  정은애 ,  김완돈

IPC: H01L21/324

CPC classification number: H01L28/55 ,  H01L28/65

Abstract: PURPOSE: A method for fabricating a capacitor of a semiconductor memory device by using a two-step heat treatment process is provided to improve a leakage current characteristic and a dielectric characteristic, by obtaining a sufficient curing effect of a dielectric layer while not oxidizing the surface of an upper electrode. CONSTITUTION: A lower electrode(20) is formed on a semiconductor substrate(10). The dielectric layer(40) is formed on the lower electrode. An upper electrode(50) made of a noble metal is formed on the dielectric layer. The first heat treatment process is performed on the resultant structure including the upper electrode in the first atmosphere including oxygen and at the first temperature within a range from 200 to 600 deg.C such that the first temperature is lower than the oxidation temperature of the upper electrode. The second heat treatment process(54) is performed on the resultant structure in the second atmosphere including oxygen and at the second temperature within a range from 300 to 900 deg.C such that the second temperature is higher than the first temperature.

Abstract translation: 目的：提供一种通过使用两步热处理来制造半导体存储器件的电容器的方法，以通过在不氧化表面的情况下获得电介质层的足够的固化效果来改善漏电流特性和介电特性 的上电极。 构成：在半导体衬底（10）上形成下电极（20）。 电介质层（40）形成在下电极上。 在电介质层上形成由贵金属制成的上电极（50）。 在包括氧的第一气氛中的上电极和第一温度在200-600℃的范围内对所得到的结构进行第一热处理工艺，使得第一温度低于上层的氧化温度 电极。 对包含氧的第二气氛中的所得结构进行第二热处理工艺（54），并且在第二温度下在第二温度为300-900℃的范围内进行第二热处理工艺（54），使得第二温度高于第一温度。

公开(公告)号：KR1020020005429A

公开(公告)日：2002-01-17

申请号：KR1020010038160

申请日：2001-06-29

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  유차영 ,  박영욱

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor memory device is provided to prevent a leakage current on an interface between a dielectric layer and the second electrode layer so that the thickness of an equivalent oxide layer of the dielectric layer is reduced, by using polysilicon to form the first electrode of a lower electrode and by using a Ru layer to form the second electrode layer of an upper electrode wherein the Ru layer has a relatively high electrical barrier. CONSTITUTION: A silicon nitride layer(40) is formed on the lower electrode. A metal oxide dielectric layer(50) is formed on the silicon nitride layer opposite to the lower electrode. The dielectric layer is formed on the lower electrode. The upper electrode composed of the Ru layer is formed on the dielectric layer.

Abstract translation: 目的：提供一种用于制造半导体存储器件的电容器的方法，以防止在电介质层和第二电极层之间的界面上的漏电流，使得电介质层的等效氧化物层的厚度通过使用 多晶硅以形成下部电极的第一电极，并且通过使用Ru层形成上部电极的第二电极层，其中Ru层具有较高的电气屏障。 构成：在下电极上形成氮化硅层（40）。 在与下电极相对的氮化硅层上形成金属氧化物电介质层（50）。 电介质层形成在下电极上。 由Ru层构成的上电极形成在电介质层上。

公开(公告)号：KR1020010026123A

公开(公告)日：2001-04-06

申请号：KR1019990037311

申请日：1999-09-03

Applicant: 삼성전자주식회사

Inventor： 김완돈 ,  유차영

IPC: H01L21/324

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor device including a hydrogen annealing process is provided to prevent a barrier layer induced into a lower portion of a storage electrode from being oxidized by crystallizing a dielectric layer in a hydrogen atmosphere of which a temperature is relatively low, and to prevent a defect such as stress damage by controlling thermal stress. CONSTITUTION: A storage electrode is formed on a semiconductor substrate. A dielectric layer is formed on the storage electrode with a high dielectric material. A plate electrode is formed on the dielectric layer. The resultant structure having the plate electrode is firstly annealed in an atmosphere including hydrogen.

Abstract translation: 目的：提供一种用于制造包括氢退火工艺的半导体器件的电容器的方法，以防止在温度为氢气的氢气氛中使介电层结晶而使感应到存储电极的下部的阻挡层被氧化 相对较低，并且通过控制热应力来防止诸如应力损伤的缺陷。 构成：存储电极形成在半导体衬底上。 在高电介质材料的存储电极上形成电介质层。 在电介质层上形成平板电极。 首先在具有氢气的气氛中退火所得到的具有平板电极的结构。

公开(公告)号：KR100255658B1

公开(公告)日：2000-05-01

申请号：KR1019950025715

申请日：1995-08-21

Applicant: 삼성전자주식회사

Inventor： 김영선 ,  심세진 ,  유차영 ,  박영욱

IPC: H01L21/108

Abstract: PURPOSE: A manufacturing method of storage electrode with HSG(Hemi-Spherical Grain) silicon layer is provided to increase cell capacitance by enlarging HSG silicon layer size, and to reduce damage of storage electrode. CONSTITUTION: A flattening layer(12) is made on a semiconductor substrate(10) after forming a transistor. Etching the flattening layer(12), a contact hole is built. A conductive layer(14), and a buffer layer is molded by depositing and patterning a conductive material and an insulating material in the contact hole. A spacer(18) is formed on both sidewalls of the buffer layer and the conductive layer(14). Using SiH4 gas and Si2H6 gas in CVP(Chemical Vapor Deposition) equipment, an HSG(Hemi-Spherical Grain) silicon layer(20) is formed on the whole structure. Through etch back process, the HSG silicon layer(20) is removed only between the storage electrodes, and the buffer layer is removed by wet-etching method.

Abstract translation: 目的：提供具有HSG（半球形晶粒）硅层的存储电极的制造方法，通过扩大HSG硅层尺寸来增加电池电容，并减少存储电极的损坏。 构成：在形成晶体管之后，在半导体衬底（10）上形成平坦化层（12）。 对平坦化层（12）进行蚀刻，构建接触孔。 通过在接触孔中沉积和图案化导电材料和绝缘材料来模制导电层（14）和缓冲层。 在缓冲层的两个侧壁和导电层（14）上形成间隔物（18）。 在CVP（化学气相沉积）设备中使用SiH4气体和Si2H6气体，在整个结构上形成HSG（半球形晶粒）硅层（20）。 通过回蚀工艺，仅在存储电极之间移除HSG硅层（20），并且通过湿蚀刻方法去除缓冲层。