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公开(公告)号：KR1020090126829A
公开(公告)日：2009-12-09
申请号：KR1020080053150
申请日：2008-06-05
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
CPC classification number: H03M13/1105 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2906 , H03M13/3738 , H03M13/3753 , H04L1/0051 , H04L1/0057
Abstract: PURPOSE: An iterative decoding method and an iterative decoding apparatus are provided to improve a bit error rate by outputting estimated values of all corresponding variable nodes as a final decoding result when a minimum number of check nodes dose not satisfy a parity check formula. CONSTITUTION: An iterative decoding method and an iterative decoding apparatus include a data buffer and a decoding block. The first estimated values corresponding to all variable nodes are stored into a buffer when an error bit number is minimum by using an iterative decoding algorithm while increasing the number of iterative decoding from one to a maximum iteration number gradually(S10-S30). The first estimated values stored in the buffer are outputted as a final decoding result when the iteration number is reached to the maximum iteration number(S40-S50).
Abstract translation: 目的：提供一种迭代解码方法和迭代解码装置，当最小数量的校验节点不满足奇偶校验公式时，通过输出所有对应的可变节点的估计值作为最终解码结果来提高误码率。 构成：迭代解码方法和迭代解码装置包括数据缓冲器和解码块。 当逐渐将迭代解码次数从1增加到最大迭代次数（S10-S30）时，通过使用迭代解码算法，当错误比特数最小时，对应于所有可变节点的第一估计值被存储到缓冲器中。 当迭代次数达到最大迭代次数时，存储在缓冲器中的第一估计值作为最终解码结果输出（S40-S50）。
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公开(公告)号：KR1020090119117A
公开(公告)日：2009-11-19
申请号：KR1020080044964
申请日：2008-05-15
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5634
Abstract: PURPOSE: A memory device and a memory data error detection method for managing the error of data stored in the memory device are provided to achieve SSD(Solid State Drive/Disk) using non-volatile memory. CONSTITUTION: A memory device(900) includes a memory cell array, a reading unit, an error correction unit and a programming unit. The memory cell array includes memory cells. The reading unit reads data from memory cells. The forward error correction unit detects the erroneous bit of data. The forward error correction unit distinguishes the memory cell in which the bit detected among memory cells is stored.
Abstract translation: 目的：提供用于管理存储在存储设备中的数据的错误的存储器件和存储器数据错误检测方法，以使用非易失性存储器来实现SSD（固态硬盘/磁盘）。 构成：存储器件（900）包括存储单元阵列，读取单元，纠错单元和编程单元。 存储单元阵列包括存储单元。 读取单元从存储单元读取数据。 前向纠错单元检测数据的错误位。 前向纠错单元区分存储单元中检测到的位的存储单元。
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公开(公告)号：KR1020090117172A
公开(公告)日：2009-11-12
申请号：KR1020080043087
申请日：2008-05-08
Applicant: 삼성전자주식회사
CPC classification number: G11C16/26 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/30
Abstract: PURPOSE: A memory device and a memory data reading method for MLC and MBC are provided to reduce time for search reading voltage level and read from the memory device by using writing voltage level. CONSTITUTION: A memory device(100) includes a memory cell array(110), a reading unit(120), and a controller(130). The memory cell array includes memory cells. The reading unit reads data from the memory cell array and uses the first reading voltage level. The reading unit produces the first index information based on data. The controller reads the second index information stored in the memory cell array.
Abstract translation: 目的：提供用于MLC和MBC的存储器件和存储器数据读取方法，以减少搜索读取电压电平的时间并通过使用写入电压电平从存储器件读取。 构成：存储器件（100）包括存储单元阵列（110），读取单元（120）和控制器（130）。 存储单元阵列包括存储单元。 读取单元从存储单元阵列读取数据并使用第一读取电压电平。 读取单元基于数据产生第一索引信息。 控制器读取存储在存储单元阵列中的第二索引信息。
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公开(公告)号：KR1020090114972A
公开(公告)日：2009-11-04
申请号：KR1020080040877
申请日：2008-04-30
Applicant: 삼성전자주식회사
IPC: H04L27/26
CPC classification number: H03M13/451 , G06F11/1072
Abstract: PURPOSE: An encoding and decoding method of multi bit level data is provided to reduce a bit error in decoding failure by using a bit - symbol mapping table having a gray code or a bit - symbol mapping table. CONSTITUTION: In an encoding and decoding method of multi bit level data, a controller receives a transmission symbol from a transmitting end(S10). A controller detects a range of the error pattern based on a table including an error pattern of a transmission symbol and transmission symbol(S12). A controller encodes at least one of a plurality of multi-bit levels corresponding to the transmission symbol based on the range of the error pattern(S14). The controller detects at least one transmission candidate symbol corresponding to the receiving symbol. The controller detects at least one transmission candidate symbol corresponding to the receiving symbol based on a table including the transmission candidate symbol.
Abstract translation: 目的：提供多位电平数据的编码和解码方法，通过使用具有灰度码或位符号映射表的位符号映射表来减少解码失败中的位错误。 构成：在多位电平数据的编码和解码方法中，控制器从发送端接收发送符号（S10）。 控制器基于包括发送符号和发送符号的错误模式的表来检测错误模式的范围（S12）。 控制器基于错误模式的范围编码与发送符号相对应的多个多位电平中的至少一个（S14）。 控制器检测与接收符号对应的至少一个传输候选符号。 控制器基于包括传输候选符号的表来检测与接收符号相对应的至少一个传输候选符号。
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公开(公告)号：KR1020090088673A
公开(公告)日：2009-08-20
申请号：KR1020080014090
申请日：2008-02-15
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1006 , G11C7/14 , G11C11/5642 , G11C29/00 , G11C29/028 , G11C29/42 , G11C29/50 , G11C2211/5634 , G11C16/26 , G11C16/30 , G11C16/3459 , G11C2211/5621
Abstract: A memory data detecting device is provided to detect the data without an error by controlling a reference voltage based on the data error due to the change of a threshold voltage of a memory cell. A first voltage comparison unit(510) compares a threshold voltage of a memory cell with a first reference voltage. A first data deciding unit(520) decides a value of the data of at least one bit or more stored in the memory cell. An error generation determining unit(530) determines the generation of the error. A reference voltage determining unit(540) determines a second reference voltage lower than the first reference voltage based on the determination result. A second data determining unit(550) re-determines the value of the data based on the second reference voltage.
Abstract translation: 提供存储器数据检测装置，通过基于由于存储单元的阈值电压的变化引起的数据误差来控制参考电压来检测数据而没有错误。 第一电压比较单元（510）将存储器单元的阈值电压与第一参考电压进行比较。 第一数据确定单元（520）确定存储在存储单元中的至少一位以上的数据的值。 错误产生确定单元（530）确定错误的生成。 参考电压确定单元（540）基于确定结果确定低于第一参考电压的第二参考电压。 第二数据确定单元（550）基于第二参考电压重新确定数据的值。
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Patent Agency Ranking
公开(公告)号：KR1020090083759A
公开(公告)日：2009-08-04
申请号：KR1020080009753
申请日：2008-01-30
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5642 , G11C16/3418 , G11C29/00
Abstract: A memory device and a memory data read method are provided to reduce the complexity of ECC(Error Control Code) decoder by applying the new multi-level reading method to a multi-level cell memory. A memory device(100) comprises a multi bit cell array(110), a programming part(120), and a controller(130). The programming part stores N data pages into the memory page(111) within the multi bit cell array, and the controller divides N data pages into the first group and the second group. The controller determines a method for reading data of the second group from the memory page after reading data of the first group from the memory page while determining the reading voltage level of data of the second group based on data which the first group reads.
Abstract translation: 提供存储器件和存储器数据读取方法，以通过将新的多电平读取方法应用于多级单元存储器来降低ECC（错误控制代码）解码器的复杂度。 存储器件（100）包括多位单元阵列（110），编程部分（120）和控制器（130）。 编程部分将N个数据页存储在多位单元阵列内的存储器页（111）中，并且控制器将N个数据页分成第一组和第二组。 控制器基于第一组读取的数据确定从存储器页读取第一组的数据之后从存储器页读取第二组的数据的方法，同时基于第一组读取的数据确定第二组的数据的读取电压电平。
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公开(公告)号：KR1020090083204A
公开(公告)日：2009-08-03
申请号：KR1020080009218
申请日：2008-01-29
Applicant: 삼성전자주식회사
CPC classification number: G11C16/34 , G11C11/5642 , G11C2211/5634
Abstract: A memory device and a memory data read method are provided to reduce an error in reading data by applying a new multi-level reading method to the multi-level cell memory. A memory device(200) comprises a multi bit cell array(210), a determination unit(220), and a buffer memory(230). The determination unit divides the multi bit cells of a memory page within the multi bit cell array into the first group and the second group, and the first group is composed of the multi bit cells having the higher threshold voltage than the reference voltage. The second group is composed of the multi bit cells having the lower-threshold voltage than the reference voltage. The determination unit updates the first and the second group through the change of the reference voltage. The buffer memory stores data about the multi bit cells of the first group and the second group.
Abstract translation: 提供存储器件和存储器数据读取方法，以通过将新的多级读取方法应用于多级单元存储器来减少读取数据中的错误。 存储器件（200）包括多位单元阵列（210），确定单元（220）和缓冲存储器（230）。 确定单元将多位单元阵列内的存储器页的多位单元划分成第一组和第二组，并且第一组由具有比参考电压更高的阈值电压的多位单元组成。 第二组由具有比参考电压低的阈值电压的多位单元组成。 确定单元通过参考电压的改变更新第一组和第二组。 缓冲存储器存储关于第一组和第二组的多位单元的数据。
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公开(公告)号：KR1020090078285A
公开(公告)日：2009-07-17
申请号：KR1020080004147
申请日：2008-01-14
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C11/5671 , G11C29/00
Abstract: A memory device and a multi bit programming method are provided to reduce complexity of the hardware by applying a new multi level programming method to a multi level cell memory when implementing an ECC(Error Control Code). A memory device includes a plurality of page buffers(131-134), a plurality of multi bit cell arrays(141-144), a data divider(110), and a selector(120). The page buffer stores the programmed data in the multi bit cell array. The data divider divides the data into the plurality of data groups. The data divider includes an encoder and a codeword divider. The encoder generates the code word by ECC-encoding the data. The selector transmits the data group to each page buffer.
Abstract translation: 提供存储器件和多位编程方法以通过在实施ECC（错误控制代码）时将新的多级编程方法应用于多级单元存储器来降低硬件的复杂度。 存储器件包括多个页缓冲器（131-134），多个多位单元阵列（141-144），数据分配器（110）和选择器（120）。 页面缓冲器将编程的数据存储在多位单元阵列中。 数据分配器将数据分割成多个数据组。 数据分频器包括编码器和码字分频器。 编码器通过对数据进行ECC编码来生成代码字。 选择器将数据组发送到每个页面缓冲区。
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公开(公告)号：KR1020090039173A
公开(公告)日：2009-04-22
申请号：KR1020070104657
申请日：2007-10-17
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5621
Abstract: An apparatus and a method of multi-bit programming is provided to form optimum distribution by using a multi-level programming method. A multi bit cell array(710) comprises a first page(711) and a second page(712). A first page comprises a plurality of first multi bit cells, and a second page comprises a plurality of second multi bit cells. A programming unit(720) programs the first and second data in the first and second multi bit cells. A verification unit(730) verifies a programming condition of first data in first multi bit cells by using the first test voltage and verifies a programming condition of the second data in second multi bit cells by taking advantage of the second test voltage. The verification unit compares the threshold voltage of first multi bit cells with the first test voltage.
Abstract translation: 提供多位编程的装置和方法，以通过使用多级编程方法来形成最佳分布。 多比特单元阵列（710）包括第一页（711）和第二页（712）。 第一页包括多个第一多位单元，第二页包括多个第二多位单元。 编程单元（720）对第一和第二多位单元中的第一和第二数据进行编程。 验证单元（730）通过使用第一测试电压来验证第一多位单元中的第一数据的编程状态，并通过利用第二测试电压来验证第二多位单元中的第二数据的编程条件。 验证单元将第一多位单元的阈值电压与第一测试电压进行比较。
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公开(公告)号：KR1020090035871A
公开(公告)日：2009-04-13
申请号：KR1020070100889
申请日：2007-10-08
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C2211/5621 , G11C2211/5648
Abstract: A programming method of non-volatile memory cell is provided to program the data more than 3 bit without using a complicated programming process. In the first and second programming levels(1,2-1,2-2), the threshold voltage of the nonvolatile memory cell belongs to one threshold voltage distribution among the first to fourth threshold voltage distributions(D1~D4) according to the first and second bit values of programming object data. In the third programming level(3-1~3-4), the threshold voltage of the nonvolatile memory cell maintains the threshold voltage at the first and second programming level according to the third bit value of data.
Abstract translation: 提供了一种非易失性存储单元的编程方法，用于在不使用复杂编程过程的情况下对3位以上的数据进行编程。 在第一和第二编程电平（1,2-1,2-2）中，非易失性存储单元的阈值电压属于第一至第四阈值电压分布（D1〜D4）中的一个阈值电压分布， 和编程对象数据的第二位值。 在第三编程电平（3-1〜3-4）中，非易失性存储单元的阈值电压根据数据的第三位值将阈值电压维持在第一和第二编程电平。
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