-
公开(公告)号：KR100416377B1
公开(公告)日：2004-01-31
申请号：KR1020010031030
申请日：2001-06-02
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L29/66598 , H01L29/66507 , H01L29/66515 , H01L29/6653 , H01L29/6656 , H01L29/6659
Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas. A method of fabricating the semiconductor transistor includes a process, where the high- and medium-concentration junction areas are formed simultaneously by the same ion-implantation step and the substrate is annealed before forming the low-concentration junction area.
Abstract translation: 本发明提供了一种使用L形间隔件的半导体晶体管及其制造方法。 半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三隔离物。 在第三隔离物和栅极图案之间以及第三隔离物和衬底之间形成L形的第四隔离物。 高浓度结区域位于第三隔离物之外的衬底中，并且低浓度结区域位于第三隔离物的水平突出部分之下。 中浓度接合区位于高浓度接合区和低浓度接合区之间。 制造半导体晶体管的方法包括一种工艺，其中通过相同的离子注入步骤同时形成高浓度和中浓度结区域，并且在形成低浓度结区域之前对衬底进行退火。
-
公开(公告)号：KR1020030093819A
公开(公告)日：2003-12-11
申请号：KR1020020031680
申请日：2002-06-05
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L21/26586 , H01L21/2807 , H01L21/28114 , H01L29/42376
Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to be capable of obtaining relatively low gate sheet resistance and restraining OWV(On-Wafer Variation) and OCV(On-Chip Variation) by using a gate structure having a negative slope. CONSTITUTION: A gate insulating layer(115) is formed on a semiconductor substrate(100). A poly-SiGe gate(130a') having a negative slope is formed on the gate insulating layer(115). At this time, the gate bottom portion has a relatively narrow width compared to the gate top portion. Also, the gate bottom portion has a relatively large Ge concentration compared to the gate top portion.
Abstract translation: 目的：提供一种半导体器件及其制造方法，其能够通过使用具有负斜率的栅极结构来获得相对低的栅极薄层电阻并且抑制OWV（On-Wafer Variation）和OCV（片上变化） 。 构成：在半导体衬底（100）上形成栅极绝缘层（115）。 在栅极绝缘层（115）上形成具有负斜率的多晶硅栅极（130a'）。 此时，栅极底部具有与栅极顶部相比较窄的宽度。 此外，与栅极顶部相比，栅极底部具有相对较大的Ge浓度。
-
公开(公告)号：KR100398874B1
公开(公告)日：2003-09-19
申请号：KR1020010072687
申请日：2001-11-21
Applicant: 삼성전자주식회사
IPC: H01L21/334
CPC classification number: H01L29/6653 , H01L21/28114 , H01L29/665 , H01L29/6656 , H01L29/7833
Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.
Abstract translation: 一种具有T形栅电极的MOS晶体管及其制造方法，其中，所述MOS晶体管包括位于半导体衬底上的T形栅电极; 设置在所述栅电极的两侧以覆盖所述半导体衬底的顶表面的L形下间隔件; 以及在栅电极两侧的半导体衬底中形成的低浓度，中浓度和高浓度杂质区。 高浓度杂质区设置在半导体衬底中与下间隔物相邻，并且中浓度杂质区设置在高浓度杂质区和低浓度杂质区之间。 根据本发明的MOS晶体管提供电容的减小，沟道长度的减小以及栅电极的横截面积的增加。 同时，中等浓度杂质区域提供了源极/漏极电阻Rsd的降低。
-
公开(公告)号：KR1020030072177A
公开(公告)日：2003-09-13
申请号：KR1020020025008
申请日：2002-05-07
Applicant: 삼성전자주식회사
IPC: H01L21/8238
CPC classification number: H01L21/2807 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02532 , H01L21/0262 , H01L29/6659
Abstract: PURPOSE: A semiconductor device having a hetero grain stack gate and a method for manufacturing the same are provided to be capable of reducing diffusion of germanium by stacking polysilicon germanium and polysilicon. CONSTITUTION: A semiconductor device comprises a semiconductor substrate(21), a gate insulating layer(22) formed on the substrate and a gate electrode formed on the gate insulating layer. The gate electrode further includes a lower poly-SiGe layer(23) having columnar crystalline structure and an upper poly-Si layer(24) having random crystalline structure. The grain size of the upper poly-Si layer(24) is larger than that of the lower poly-SiGe layer(23).
Abstract translation: 目的：提供具有异质晶粒堆叠栅极的半导体器件及其制造方法，以能够通过堆叠多晶硅锗和多晶硅来减少锗的扩散。 构成：半导体器件包括半导体衬底（21），形成在衬底上的栅极绝缘层（22）和形成在栅极绝缘层上的栅电极。 栅电极还包括具有柱状晶体结构的下多晶硅层（23）和具有无规晶体结构的上多晶硅层（24）。 上部多晶硅层（24）的晶粒尺寸大于下部多晶硅层（23）的晶粒尺寸。
-
公开(公告)号：KR1020020080111A
公开(公告)日：2002-10-23
申请号：KR1020010019304
申请日：2001-04-11
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L21/823857 , H01L21/823842
Abstract: PURPOSE: A method for forming a CMOS(Complementary Metal Oxide Semiconductor) device having a dual gate is provided to prevent the depletion of a poly-gate, to reduce a threshold voltage and to improve the reliability of a gate oxide. CONSTITUTION: A PMOS transistor region(114) and an NMOS transistor region(112) are formed in a silicon substrate by ion-implanting processes, respectively. After forming an isolation layer(116), a gate oxide is grown on the silicon substrate(100) by thermal oxidation. Then, a gate electrode(123) on which a tungsten nitride, a molybdenum film and a tungsten film are sequentially stacked is formed at the PMOS transistor region(114). Also, a gate electrode(133) on which a molybdenum film and a tungsten film are sequentially stacked is formed at the NMOS transistor region(112).
Abstract translation: 目的：提供一种用于形成具有双栅极的CMOS（互补金属氧化物半导体）器件的方法，以防止多栅极的耗尽，降低阈值电压并提高栅极氧化物的可靠性。 构成：分别通过离子注入工艺在硅衬底中形成PMOS晶体管区域（114）和NMOS晶体管区域（112）。 在形成隔离层（116）之后，通过热氧化在硅衬底（100）上生长栅极氧化物。 然后，在PMOS晶体管区域（114）上形成依次层叠有氮化钨，钼膜和钨膜的栅电极（123）。 此外，在NMOS晶体管区域（112）形成有依次层叠有钼膜和钨膜的栅电极（133）。
-
Patent Agency Ranking
公开(公告)号：KR100304688B1
公开(公告)日：2001-11-30
申请号：KR1019940003979
申请日：1994-02-28
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A fabrication method of semiconductor devices is provided to improve a reliability of the device by removing F(Fluorine) elements from a tungsten silicide layer after removing contaminated materials on the surface of the tungsten silicide layer and performing a thermal treatment. CONSTITUTION: An oxide(11) is formed on a substrate(10) by a thermal oxidation. A polysilicon layer(12) is formed on the entire surface of the resultant structure. A tungsten silicide layer(13) is formed on the polysilicon layer(12) by CVD(Chemical Vapour Deposition) using WF6 and SiH4 as a reaction gas. At this time, contaminated materials are removed from the tungsten silicide layer(13). Fluorine elements are then removed from the tungsten silicide layer(13) to the free surface of the tungsten silicide layer(13) by an outdiffusion through a thermal treatment.
-
公开(公告)号：KR100138308B1
公开(公告)日：1998-06-01
申请号：KR1019940034250
申请日：1994-12-14
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L23/485 , H01L21/28061 , H01L21/76805 , H01L23/5226 , H01L23/53271 , H01L29/4925 , H01L29/4933 , H01L29/4983 , H01L2924/0002 , Y10S257/905 , Y10S257/906 , Y10S257/907 , Y10S257/908 , H01L2924/00
Abstract: 상부도전층과 하부도전층의 접촉 구조 및 그 방법에 대해 기재되어 있다. 이는 제1 도전층과 제1 실리사이드층이 적층된 구조의 하부도전층과 불순물이 도우프된 제2 도전층과 제2 실리사이드층이 적층된 구조의 상부도전층의 접촉구조에 있어서, 상기 제1 도전층과 상기 제2 도전층이 직접적으로 접촉하는 것을 특징으로 한다. DRAM에 있어서, 워드라인과 비트라인의 접촉구조에 해당한다. 따라서, 하부도전층과 상부도전층의 접촉 저항을 저하시켜, 소자의 전기적 특성을 향상시킨다.
-
公开(公告)号：KR1019960026953A
公开(公告)日：1996-07-22
申请号：KR1019940038281
申请日：1994-12-28
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L29/423
Abstract: 3층구조의 게이트전극 및 그 형성방법에 관하여 기쟈되고 있다.
이는 반도체기판 상에 형성된 게이트산화막, 상기 게이트산화막 상에 형성된 다결정실리콘막, 상기 다결정실리콘막 상에 형성된 장벽급속층, 및 상기 장벽금속층 상에 형성된 저저항금속층을 포함하는 것을 특징으로 한다. 따라서 게이트전극의 전기적 특성 및 신뢰도를 향상시킬 수 있다. -
-
-
-
-
-
-
-
Search Results
173
records
(took 0.026 seconds)
