公开(公告)号：KR100432885B1

公开(公告)日：2004-05-22

申请号：KR1020020001470

申请日：2002-01-10

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  이수근 ,  박기관 ,  이경우

IPC: H01L21/3205

Abstract: PURPOSE: A method for forming an interlayer dielectric pattern is provided to be capable of finely forming an opening portion and securing the vertical profile of the opening portion by using a spacer as an etching mask and using an organic polymer layer as the interlayer dielectric. CONSTITUTION: After forming a conductive layer pattern(110) at the upper portion of a semiconductor substrate, an interlayer dielectric and a hard mask layer are sequentially deposited on the entire surface of the resultant structure. Then, a hard mask pattern having the first opening portion(171) is formed by selectively patterning the hard mask layer for exposing the upper surface of the interlayer dielectric. A spacer(190) is formed at both sidewalls of the first opening portion. The upper surface of the conductive layer pattern is exposed by selectively etching the resultant structure using the spacer as an etching mask. Preferably, the interlayer dielectric is made of at least one selected from a group consisting of an organic polymer layer, a fluorine doped oxide layer, a carbon doped oxide layer, and a silicon oxide layer.

Abstract translation: 目的：提供一种用于形成层间电介质图案的方法，其能够通过使用间隔物作为蚀刻掩模并使用有机聚合物层作为层间电介质来精细地形成开口部分并且确保开口部分的垂直轮廓。 构成：在半导体衬底的上部形成导电层图形（110）之后，在所得结构的整个表面上顺序沉积层间电介质和硬掩模层。 然后，通过选择性地图案化硬掩模层来形成具有第一开口部分（171）的硬掩模图案以暴露层间电介质的上表面。 间隔物（190）形成在第一开口部分的两个侧壁处。 通过使用隔离物作为蚀刻掩模选择性地蚀刻所得结构来暴露导电层图案的上表面。 优选地，层间电介质由选自由有机聚合物层，氟掺杂氧化物层，碳掺杂氧化物层和氧化硅层组成的组中的至少一种制成。

公开(公告)号：KR1020040034318A

公开(公告)日：2004-04-28

申请号：KR1020030003296

申请日：2003-01-17

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  박완재 ,  안정훈 ,  이경태 ,  정무경 ,  이용준 ,  김일구 ,  이수근

IPC: H01L27/04

CPC classification number: H01L28/55 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/1085 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: An MIM(Metal-Insulator-Metal) capacitor having high capacitance, an IC(Integrated Circuit) chip having the same, a manufacturing method thereof are provided to be capable of minimizing the thickness of a dielectric layer while securing the reliability of the dielectric layer. CONSTITUTION: An MIM capacitor includes the first and second line(112,114) isolated from each other on a substrate. At this time, the first and second voltage are applied to the first and second line, respectively. The MIM capacitor further includes a lower electrode(120) isolated from the first line and connected with the second line, and an upper electrode(140) overlapped with the lower electrode and connected with the first line. At this time, a dielectric layer is located between the lower and upper electrode.

Abstract translation: 目的：具有高电容的MIM（金属 - 绝缘体 - 金属）电容器，具有该电容器的IC（集成电路）芯片）及其制造方法被设置为能够使电介质层的厚度最小化，同时确保 电介质层。 构成：MIM电容器包括在衬底上彼此隔离的第一和第二线（112,114）。 此时，第一和第二电压分别施加到第一和第二线。 MIM电容器还包括与第一线隔离并与第二线相连的下电极（120）和与下电极重叠并与第一线连接的上电极（140）。 此时，电介质层位于下电极和上电极之间。

公开(公告)号：KR100416596B1

公开(公告)日：2004-02-05

申请号：KR1020010025573

申请日：2001-05-10

Applicant: 삼성전자주식회사

Inventor： 이수근 ,  신홍재 ,  이경우 ,  김재학

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.

Abstract translation: 提供了一种在半导体器件中形成互连线的方法。 第一蚀刻停止层形成在形成于半导体衬底上的下导电层上。 在第一蚀刻阻挡层上形成第一层间绝缘层。 在第一层间绝缘层上形成第二蚀刻阻挡层。 在第二蚀刻阻挡层上形成第二层间绝缘层。 使用第一蚀刻停止层作为蚀刻停止点依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下部导电层对齐的过孔。 形成保护层以保护暴露在通孔底部的第一蚀刻阻挡层的一部分。 使用第二蚀刻停止层蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点以形成连接到通孔的沟槽。 保护层被移除。 位于通孔底部的第一蚀刻停止层部分被去除。 形成填充通孔和沟槽并电连接到下导电层的上导电层。

公开(公告)号：KR1020030093721A

公开(公告)日：2003-12-11

申请号：KR1020020031547

申请日：2002-06-05

Applicant: 삼성전자주식회사

Inventor： 이광희 ,  정현담 ,  이경우 ,  이수근

IPC: H01L21/3205

CPC classification number: H01L21/76825 ,  H01L21/76808 ,  H01L21/76814

Abstract: PURPOSE: A method for forming a pattern of an intermetal dielectric layer is provided to be capable of preventing the generation of photoresist residuals after carrying out a developing process by changing the chemical structure of the surface of a via hole using UV(UltraViolet) ray. CONSTITUTION: After sequentially forming a lower etching stop layer(2), a lower insulating layer(3), an upper etching stop layer(4), and an upper insulating layer(5) at the upper portion of a lower line(1) formed semiconductor substrate, a via hole is formed by selectively patterning the upper insulating layer, the upper etching stop layer, and the lower insulating layer for exposing the lower etching stop layer. Then, UV ray is irradiated to the via hole. After forming a photoresist layer(8) on the entire surface of the resultant structure, a photoresist pattern is formed by selectively patterning the photoresist layer.

Abstract translation: 目的：提供一种用于形成金属间电介质层的图案的方法，其能够通过使用UV（UltraViolet）光线改变通孔的表面的化学结构来防止在进行显影处理之后产生光致抗蚀剂残留物。 构成：在下线（1）的上部依次形成下蚀刻停止层（2），下绝缘层（3），上蚀刻停止层（4）和上绝缘层（5） 形成的半导体衬底，通过选择性地图案化上绝缘层，上蚀刻停止层和下绝缘层形成通孔，用于暴露下蚀刻停止层。 然后，将紫外线照射到通孔。 在所得结构的整个表面上形成光致抗蚀剂层（8）之后，通过选择性地图案化光致抗蚀剂层来形成光致抗蚀剂图案。

公开(公告)号：KR1020020045494A

公开(公告)日：2002-06-19

申请号：KR1020010036933

申请日：2001-06-27

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  신홍재 ,  이수근 ,  이경우

IPC: H01L21/283

Abstract: PURPOSE: A method for forming a semiconductor device having low permittivity interlayer dielectric is provided to exactly form a micro pattern on a SiOC layer and to restrain a parasitic capacitance between interconnections or contact plugs by using the SiOC layer having a low dielectric constant. CONSTITUTION: A low permittivity carbon oxide silicon layer made of SiOC is formed on a substrate(100) by a CVD(Chemical Vapour Deposition) using a nitrogen included gas as a source gas or a carrier gas. A plasma processing is performed on the carbon oxide silicon layer by supplying gases, such as a helium, a hydrogen, an N2O, or an Ar gas to a processing chamber. A photoresist is deposited and patterned on the plasma processed carbon oxide silicon layer(111).

Abstract translation: 目的：提供一种形成具有低介电常数层间电介质的半导体器件的方法，以在SiOC层上精确地形成微图案，并通过使用具有低介电常数的SiOC层来抑制互连或接触插塞之间的寄生电容。 构成：使用含氮气体作为原料气体或载气，通过CVD（化学气相沉积）在基板（100）上形成由SiOC制成的低介电常数碳氧化硅层。 通过向处理室供给诸如氦气，氢气，N 2 O或Ar气体的气体，对碳氧化硅硅层进行等离子体处理。 在等离子体处理的碳氧化硅层（111）上沉积并图案化光致抗蚀剂。

公开(公告)号：KR1020020012106A

公开(公告)日：2002-02-15

申请号：KR1020000070973

申请日：2000-11-27

Applicant: 삼성전자주식회사

Inventor： 김원진 ,  이수근 ,  신홍재 ,  한재현 ,  김재학 ,  강호규

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing an interconnection using a hydrogen silsesquioxane(HSQ) layer as an interlayer dielectric is provided to simplify a process for forming the interconnection, by performing a plasma treatment regarding the HSQ layer so that the HSQ layer is not damaged in a photolithography process to directly pattern the HSQ layer. CONSTITUTION: A low dielectric layer is formed on a semiconductor substrate(10). A plasma treatment process is performed regarding the entire surface of the low dielectric layer. The plasma-treated low dielectric layer is patterned to form an opening exposing a predetermined region of the semiconductor substrate. A conductive layer filling the opening is formed on the entire surface of the semiconductor substrate.

Abstract translation: 目的：提供一种使用氢倍半硅氧烷（HSQ）层作为层间电介质制造互连的方法，以简化形成互连的工艺，通过对HSQ层进行等离子体处理，使得HSQ层在 光刻工艺直接对HSQ层进行图案化。 构成：在半导体衬底（10）上形成低介电层。 对低介电层的整个表面进行等离子体处理。 将等离子体处理的低介电层图案化以形成暴露半导体衬底的预定区域的开口。 填充开口的导电层形成在半导体衬底的整个表面上。

公开(公告)号：KR100251721B1

公开(公告)日：2000-10-02

申请号：KR1019970073497

申请日：1997-12-24

Applicant: 삼성전자주식회사

Inventor： 이수근 ,  김영석

IPC: H04M3/42

Abstract: PURPOSE: A CT-2 destination matching switching system for providing terminating service and a controlling method thereof are provided to support a meet-me function, conference function and recording function by using VMS(Voice Mailing System) connected to an existing public radio paging network, and receive an incoming telephone in CT-2 network by using the meet-me function. CONSTITUTION: A PSTN(Public Switched telephone network) matching part(111) performs a function for connecting a public telecommunication network and various trunks of incoming call and outgoing call. A CT-2 matching part(112) processes various calls of CT-2, and transforms a number of CT-2 subscriber to a PAGER number of receiver. A paging exchange matching part(113) performs a paging originating function via No.7 signalling system and TNPP protocol. A VMS matching part(114) is matched to the VMS, performs a meet-me function and various application and maintenance functions, and accepts a terminating system. A X.25 matching part transmits CAMA(Centralized Automatic Message Account) accounting data to CT-2 network management device by using X.25 protocol. A controlling part(116) collectively controls the system.

Abstract translation: 目的：提供一种用于提供终端服务的CT-2目的地匹配交换系统及其控制方法，通过使用连接到现有公共无线寻呼网络的VMS（语音邮件系统）来支持会议功能，会议功能和记录功能 ，并通过使用会议功能在CT-2网络中接收电话。 构成：PSTN（公共交换电话网）匹配部分（111）执行连接公共电信网络和各种呼入呼叫和呼出呼叫的中继线的功能。 CT-2匹配部分（112）处理CT-2的各种呼叫，并将多个CT-2用户转换为接收机的PAGER号码。 寻呼交换机匹配部分（113）通过No.7信令系统和TNPP协议执行寻呼发起功能。 VMS匹配部分（114）与VMS匹配，执行会议功能和各种应用和维护功能，并接受终止系统。 X.25匹配部分使用X.25协议将CAMA（集中自动消息账号）计费数据发送到CT-2网络管理设备。 控制部（116）共同控制系统。

公开(公告)号：KR1020000040316A

公开(公告)日：2000-07-05

申请号：KR1019980055904

申请日：1998-12-17

Applicant: 삼성전자주식회사

Inventor： 김민 ,  이수근

IPC: H01L21/30

Abstract: PURPOSE: A manufacturing method of protective film is to plug a void resulted from a gap between metallic patterns in a passivation process, thereby preventing the protective film from being damaged in a subsequent photolithography process. CONSTITUTION: A manufacturing method of protective film comprise the steps of: vacuum depositing a first insulating layer(104) having an excellent step coverage on the upper part of a semiconductor substrate(100) on which a plural metallic patterns(102) are formed; vacuum depositing a second insulating layer(106) onto the first insulating layer, followed by vacuum depositing a third insulating layer(108) having an excellent step coverage on the second insulating layer to eliminate a void present in between the plural metallic patterns.

Abstract translation: 目的：保护膜的制造方法是在钝化过程中堵塞由金属图案之间的间隙产生的空隙，从而防止在随后的光刻工艺中保护膜被损坏。 构成：保护膜的制造方法包括以下步骤：在其上形成有多个金属图案（102）的半导体衬底（100）的上部真空沉积具有优异阶梯覆盖的第一绝缘层（104）; 将第二绝缘层（106）真空沉积到第一绝缘层上，然后在第二绝缘层上真空沉积具有优异阶梯覆盖的第三绝缘层（108），以消除存在于多个金属图案之间的空隙。

公开(公告)号：KR1020000001569A

公开(公告)日：2000-01-15

申请号：KR1019980021909

申请日：1998-06-12

Applicant: 삼성전자주식회사

Inventor： 오혁상 ,  이수근 ,  서태욱

IPC: H01L21/28

Abstract: PURPOSE: A metal wiring method using damascene technique is provided to prevent an electrical short between adjacent conductive layers when interconnections. CONSTITUTION: The method comprises the steps of: forming an insulating layer(114) on a semiconductor substrate(100) having transistors; forming an etch stopping layer(118) having excellent etching selectivity compared to the insulating layer(114); forming a trench(120) by etching the portion of the insulating layer(114) and the etch stopping layer(118); forming a via contact hole(122) to expose the semiconductor substrate by etching the remained insulating layer; removing a native oxide(124) exposed on the substrate by RF(radio frequency) sputtering; and forming a metal wire(116) by filling metal materials into the trench(120) and the via contact hole(122) and by flattening the metal materials using CMP(chemical mechanical polishing).

Abstract translation: 目的：提供使用镶嵌技术的金属布线方法，以防止互连时相邻导电层之间的电短路。 构成：该方法包括以下步骤：在具有晶体管的半导体衬底（100）上形成绝缘层（114）; 形成与绝缘层（114）相比具有优异蚀刻选择性的蚀刻停止层（118）; 通过蚀刻绝缘层（114）的部分和蚀刻停止层（118）形成沟槽（120）; 形成通孔接触孔（122），通过蚀刻剩余的绝缘层来露出半导体衬底; 通过RF（射频）溅射去除在衬底上暴露的天然氧化物（124）; 以及通过将金属材料填充到所述沟槽（120）和所述通孔接触孔（122）中并通过使用CMP（化学机械抛光）使所述金属材料变平而形成金属线（116）。

公开(公告)号：KR1020000000582A

公开(公告)日：2000-01-15

申请号：KR1019980020261

申请日：1998-06-01

Applicant: 삼성전자주식회사

Inventor： 이승재 ,  서태욱 ,  이수근

IPC: H01L21/28

Abstract: PURPOSE: A forming method of boardless contact is provided to prevent a damage of an insulating layer formed at lower portion of an upper contact hole when the size of the upper contact hole is larger than that of a lower contact hole. CONSTITUTION: The method comprises the steps of: forming a first insulating layers(102,104,106) on a semiconductor substrate(100); forming an etch stopping layer(108) on the first insulating layers by depositing a material having high etching selectivity compared to the first insulating layers; forming a lower contact hole(110) by etching the etch stopping layer(108) and the first insulating layers(102,104,106); plugging a first metal into the lower contact hole in order to form a metal contact(112); forming a second insulating layer(118) on resultant structure; forming an upper contact hole(120) by etching the second insulating layer(118) to expose the metal contact(112); and plugging a second metal into the upper contact hole(120) to form a via contact(122).

Abstract translation: 目的：当上接触孔的尺寸大于下接触孔的尺寸时，提供无板接触的形成方法，以防止在上接触孔的下部形成的绝缘层的损坏。 构成：该方法包括以下步骤：在半导体衬底（100）上形成第一绝缘层（102,104,106）; 通过与第一绝缘层相比沉积具有高蚀刻选择性的材料在第一绝缘层上形成蚀刻停止层（108）; 通过蚀刻蚀刻停止层（108）和第一绝缘层（102,104,106）形成下接触孔（110）; 将第一金属插入下接触孔中以形成金属接触件（112）; 在所得结构上形成第二绝缘层（118）; 通过蚀刻所述第二绝缘层（118）以暴露所述金属触点（112）形成上接触孔（120）; 以及将第二金属插入所述上接触孔（120）以形成通孔接触（122）。