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公开(公告)号：KR1020100004248A
公开(公告)日：2010-01-13
申请号：KR1020080064318
申请日：2008-07-03
Applicant: 삼성전기주식회사
IPC: H05K1/18
CPC classification number: H01L2224/04105 , H01L2224/19 , H01L2924/14 , H01L2924/00 , H01L2924/00012
Abstract: PURPOSE: A method of manufacturing a printed circuit board comprising embedded electronic component therein is provided to match an external connection bump of an electronic component to a via of an external circuit layer by aligning the external connection bump of the electric component to an upper circuit pattern of a base substrate. CONSTITUTION: A base substrate(100) comprises a cavity(170) and an alignment mark. The base substrate is one side PCB(Printed Circuit Board), both-side PCB or a multi-layer PCB. An external connection bump(330) is formed on the one-side of the electric component(300). A position detection unit(500) detects the location of the external connection bump and the alignment mark. The position detection unit includes an infrared camera or a sensor. The electric component is installed on the base substrate so that the external connection bump is arranged with the alignment mark.
Abstract translation: 目的：提供一种制造其中包括嵌入式电子部件的印刷电路板的方法，以通过将电气部件的外部连接凸起与上部电路图案对准来将电子部件的外部连接凸块与外部电路层的通孔相匹配 的基底。 构成：基底（100）包括空腔（170）和对准标记。 基底是单面PCB（印刷电路板），双面PCB或多层PCB。 在电气部件（300）的一侧形成有外部连接突起（330）。 位置检测单元（500）检测外部连接凸起和对准标记的位置。 位置检测单元包括红外相机或传感器。 电气部件安装在基底基板上，使得外部连接凸起布置有对准标记。
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公开(公告)号：KR1020100000168A
公开(公告)日：2010-01-06
申请号：KR1020080059560
申请日：2008-06-24
Applicant: 삼성전기주식회사
IPC: H01L21/68 , H01L23/544
CPC classification number: H01L23/544 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L24/02 , H01L24/16 , H01L24/25 , H01L24/82 , H01L2223/54426 , H01L2224/0231 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/19 , H01L2224/83121 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K1/0269 , H05K1/185 , H05K3/4602 , H05K3/4679 , H05K2201/09918
Abstract: PURPOSE: A semiconductor chip having an align mark and a method for manufacturing the same are provided to obtain good electrical connection of the printed circuit board and semiconductor chip. CONSTITUTION: The semiconductor chip(10) having the alignment mark comprises the outside connection bump(300) and alignment mark(500). The outside connection bump is arranged in the single-side (one surface) of the semiconductor chip. The outside connection bump draws out the signal of the electronic circuit from the semiconductor chip. The alignment mark is arranged in the other side of the semiconductor chip. The alignment mark has the location information of the outside connection bump.
Abstract translation: 目的：提供具有对准标记的半导体芯片及其制造方法，以获得印刷电路板和半导体芯片的良好电连接。 构成：具有对准标记的半导体芯片（10）包括外部连接凸起（300）和对准标记（500）。 外部连接凸块布置在半导体芯片的单面（一个表面）中。 外部连接凸块从半导体芯片上抽出电子电路的信号。 对准标记布置在半导体芯片的另一侧。 对准标记具有外部连接凸块的位置信息。
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公开(公告)号：KR1020090126537A
公开(公告)日：2009-12-09
申请号：KR1020080052675
申请日：2008-06-04
Applicant: 삼성전기주식회사
CPC classification number: H05K1/185 , H01L23/3121 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/24227 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0106 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H05K3/4602 , H05K2201/0394 , H05K2201/10674 , H05K2201/10969 , Y10T29/49171
Abstract: PURPOSE: A printed circuit board with electronic components embedded therein and a method for fabricating the same are provided to reduce manufacturing costs and simplify manufacturing process by installing an electronic component on a metal layer. CONSTITUTION: In a device, a core substrate includes a supporting metal layer(106) formed on a single-side of an insulating resin layer(102) in which a cavity is punched, and it also includes an internal layer circuit layer formed in both sides of the insulating resin layer. An electronic component(109) is built in the cavity while being supported by the metal supporting layer. A build-up layer(115) includes an insulating layer formed on both sides of the core substrate and an external circuit layer(114). The electronic component is mounted in the device while facing to upwardly. The electronic component is fixed on the supporting metal layer by using an adhesive material. The adhesive material is a silicon rubber plate or a polyimide adhesive tape.
Abstract translation: 目的：提供一种嵌有电子部件的印刷电路板及其制造方法，以通过在金属层上安装电子部件来降低制造成本并简化制造工艺。 构成：在器件中，芯基板包括形成在绝缘树脂层（102）的单侧上的支撑金属层（106），其中冲压空腔，并且还包括形成在两者中的内层电路层 绝缘树脂层的侧面。 电子部件（109）由金属支撑层支撑在内腔中。 堆积层（115）包括形成在芯基板的两侧上的绝缘层和外部电路层（114）。 电子部件安装在设备中同时向上。 通过使用粘合剂材料将电子部件固定在支撑金属层上。 粘合剂材料是硅橡胶板或聚酰亚胺胶带。
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公开(公告)号：KR1020090021605A
公开(公告)日：2009-03-04
申请号：KR1020070086244
申请日：2007-08-27
Applicant: 삼성전기주식회사
IPC: H01L27/04
CPC classification number: H01L23/49822 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/50 , H01L23/642 , H01L24/45 , H01L24/48 , H01L2224/32225 , H01L2224/45139 , H01L2224/4824 , H01L2224/73215 , H01L2924/00011 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/18165 , H01L2924/19015 , H01L2924/19041 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2924/01049
Abstract: A semiconductor memory package is provided to minimize the parasitic inductance by using the decoupling capacitor of the thin film type. Decoupling capacitors(130a,130b) of the single layer structure are formed in a semiconductor memory package(100). The package comprises a substrate(110). A memory chip(140) is mounted on the one side of the substrate. A plate wiring(160), a solder ball(170) and a solder resist(120) are formed on the other side of substrate. A bonding layer(142) is formed between the one side of substrate and the memory chip. A window(116) is formed on the center of the region having the memory chip. The memory chip is connected to a plate wiring(160) which are formed on the other side of the substrate. The epoxy(150) charges the window and protects the wire.
Abstract translation: 提供半导体存储器封装以通过使用薄膜类型的去耦电容器来最小化寄生电感。 单层结构的去耦电容器（130a，130b）形成在半导体存储器封装（100）中。 所述包装件包括基底（110）。 存储芯片（140）安装在基板的一侧。 在基板的另一侧上形成板状配线（160），焊球（170）和阻焊剂（120）。 在衬底的一侧和存储器芯片之间形成结合层（142）。 在具有存储芯片的区域的中心上形成窗口（116）。 存储芯片连接到形成在基板的另一侧上的板状配线（160）。 环氧树脂（150）为窗户充电并保护电线。
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公开(公告)号：KR100850755B1
公开(公告)日：2008-08-06
申请号：KR1020070032293
申请日：2007-04-02
Applicant: 삼성전기주식회사
Abstract: A manufacturing method for a capacitor embedded printed circuit board is provided to realize water dispersion or organic dispersion thin conductive layer by drying after coating the water dispersion or organic dispersion thin conductive layer on a lower electrode. A manufacturing method for a capacitor embedded printed circuit board includes the steps of: forming a lower electrode(10); forming a conductive polymer layer(20) by coating conductive polymer on the lower electrode; forming a dielectric layer(30) on the conductive polymer layer; and forming an upper electrode(40) on the dielectric layer, wherein the conductive polymer layer is one of water dispersion conductive polymer layer and organic dispersion conductive polymer layer.
Abstract translation: 提供了一种用于电容器嵌入式印刷电路板的制造方法，用于通过在下电极上涂布水分散体或有机分散体薄导电层之后通过干燥实现水分散或有机分散薄导电层。 电容器嵌入式印刷电路板的制造方法包括以下步骤：形成下电极（10）; 通过在下电极上涂覆导电聚合物形成导电聚合物层（20）; 在所述导电聚合物层上形成介电层（30）; 以及在所述电介质层上形成上电极（40），其中所述导电聚合物层是水分散导电聚合物层和有机分散体导电聚合物层之一。
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Patent Agency Ranking
公开(公告)号：KR100835660B1
公开(公告)日：2008-06-09
申请号：KR1020060100955
申请日：2006-10-17
Applicant: 삼성전기주식회사
Abstract: 커패시터, 그 제조방법 및 커패시터가 내장된 인쇄회로기판이 개시된다. 인쇄회로기판에 내장되는 커패시터(capacitor)로서, 제1 전극층; 일면이 상기 제1 전극층과 대향하며, 타면에만 돌기가 형성되는 제2 전극층 및; 상기 제1 전극층과 상기 제2 전극층 사이에 개재되는 유전층을 포함하는 커패시터는, 커패시터와 절연층과의 접합 면에 돌기를 형성함으로써, 커패시터와 절연층 사이의 향상된 접착력을 제공할 수 있다.
인쇄회로기판, 내장, 커패시터, 돌기-
公开(公告)号：KR100835086B1
公开(公告)日：2008-06-03
申请号：KR1020070009442
申请日：2007-01-30
Applicant: 삼성전기주식회사
IPC: H01L21/8242
Abstract: A method of manufacturing a thin film capacitor and a thin film capacitor-embedded printed circuit board is provided to simplify process equipment and to manufacture the thin film capacitor with low cost. A method of manufacturing a thin film capacitor includes: forming a dielectric layer(120) on a lower electrode(110); a first pattern portion(130) at a partial region of the dielectric layer; forming a plating seed layer(140) on an exposed region of the first pattern portion and the dielectric layer; forming a second pattern portion on the plating seed layer, which is formed on the first pattern portion; plating a laminate body in which the second pattern portion is formed; and removing the first pattern portion, the second pattern portion, and the plating seed layer in the first and second pattern portions.
Abstract translation: 提供制造薄膜电容器和薄膜电容器嵌入式印刷电路板的方法，以简化工艺设备并以低成本制造薄膜电容器。 制造薄膜电容器的方法包括：在下电极（110）上形成电介质层（120）; 在所述电介质层的部分区域处的第一图案部分（130）; 在所述第一图案部分和所述电介质层的暴露区域上形成电镀种子层（140）; 在所述电镀种子层上形成形成在所述第一图案部分上的第二图案部分; 电镀其中形成有第二图案部分的层压体; 以及在第一和第二图案部分中去除第一图案部分，第二图案部分和电镀种子层。
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公开(公告)号：KR1020080034691A
公开(公告)日：2008-04-22
申请号：KR1020060100955
申请日：2006-10-17
Applicant: 삼성전기주식회사
Abstract: A capacitor, a manufacturing method thereof, and a printed circuit board with the capacitor are provided to improve adhesion force between the capacitor and an insulation layer. A printed circuit board includes a first electrode layer, a second electrode layer, a dielectric layer(20), and an insulation layer. One surface of the second electrode layer is opposed to the first electrode layer. A protrusion(15) is formed on the other surface of the second electrode layer. The dielectric layer is interposed between the first electrode layer and the second electrode layer. The protrusion is made of the same material as the second electrode. The protrusion is formed in plural. The plurality of protrusions is arranged at a regular interval. The protrusion is formed through electrolyte plating. The insulation layer is stacked on the other surface of the second electrode layer.
Abstract translation: 提供电容器，其制造方法和具有电容器的印刷电路板，以提高电容器和绝缘层之间的粘附力。 印刷电路板包括第一电极层，第二电极层，电介质层（20）和绝缘层。 第二电极层的一个表面与第一电极层相对。 在第二电极层的另一个表面上形成突起（15）。 电介质层介于第一电极层和第二电极层之间。 突起由与第二电极相同的材料制成。 突起形成为多个。 多个突起以规则间隔排列。 突起通过电解电镀形成。 绝缘层堆叠在第二电极层的另一个表面上。
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公开(公告)号：KR100793916B1
公开(公告)日：2008-01-15
申请号：KR1020060031099
申请日：2006-04-05
Applicant: 삼성전기주식회사
CPC classification number: H04R19/00 , H05K1/162 , H05K2201/0175 , H05K2201/0179 , H05K2201/0355 , H05K2201/09309 , H05K2203/0346 , H05K2203/0353 , Y10T29/417 , Y10T29/42 , Y10T29/43 , Y10T29/435
Abstract: 본 발명은 인쇄회로기판 내장형 커패시터의 제조방법에 관한 것으로서, 특히, 보강기재 및 그 양면에 적층된 동박으로 이루어진 CCL 기판을 준비하는 단계와, 상기 CCL 기판의 동박 표면을 평탄화하는 단계와, 상기 평탄화된 CCL 기판을 순차적으로 세정 및 건조하는 단계와, 상기 세정 및 건조된 동박 표면 상에 유전층을 형성하는 단계 및 상기 유전층 상에 상부전극을 형성하는 단계를 포함하는 인쇄회로기판 내장형 커패시터의 제조방법에 관한 것이다.
내장형 커패시터, CCL, 동박, 결함, 평탄화, 연마-
公开(公告)号：KR100735339B1
公开(公告)日：2007-07-04
申请号：KR1020060137585
申请日：2006-12-29
Applicant: 삼성전기주식회사
IPC: H01L27/105 , H01L21/3205
Abstract: A method for manufacturing a circuit board embedding a thin film capacitor is provided to prevent the generation of a damage region formed in a dielectric when a laser is irradiated by using a sacrificial layer. A sacrificial layer(12) is formed on a first substrate(11). A dielectric(14) is formed on the sacrificial layer. A first electrode layer(16) is formed on the dielectric. The first substrate is arranged on a second substrate(21) so that the first electrode layer is connected to an upper surface of the second substrate. A laser beam is irradiated to the sacrificial layer through the first substrate to disassemble the sacrificial layer. The first substrate is separated from the second substrate. A second electrode layer is formed on the dielectric.
Abstract translation: 提供一种用于制造嵌入薄膜电容器的电路板的方法，以防止当使用牺牲层照射激光时在电介质中形成损伤区域的产生。 牺牲层（12）形成在第一基板（11）上。 介电层（14）形成在牺牲层上。 第一电极层（16）形成在电介质上。 第一基板布置在第二基板（21）上，使得第一电极层连接到第二基板的上表面。 激光束通过第一基板照射到牺牲层，以分解牺牲层。 第一衬底与第二衬底分离。 在电介质上形成第二电极层。
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