-
公开(公告)号：KR1020130035002A
公开(公告)日：2013-04-08
申请号：KR1020110099200
申请日：2011-09-29
Applicant: 한국과학기술원
CPC classification number: H01L2224/11 , H01L2224/1134 , H01L2224/13144 , H01L2924/07802 , H01L2924/07811 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
Abstract: PURPOSE: A bump electrode structure of a semiconductor device and a manufacturing method thereof are provided to prevent a short phenomenon, to secure the insulation property of a non-conductive adhesive, and to obtain the high reliability of an anisotropic conductive adhesive in a fine pitch condition. CONSTITUTION: A bump(120) is formed on the upper side of a semiconductor(110). At least one or more protruding cores(130) are formed on the upper side of the bump and are made of polymer materials with a thermosetting property or a thermoplastic property. The width of the protruding core is 1 to 10 um. A metal layer(150) is formed on the upper sides of the protruding core and the bump. The metal layer is contacted with an electrode of a substrate or another semiconductor device.
Abstract translation: 目的：提供一种半导体器件的凸块电极结构及其制造方法，以防止短路现象，确保非导电性粘合剂的绝缘性，并且以精细间距获得各向异性导电粘合剂的高可靠性 条件。 构成：在半导体（110）的上侧形成凸块（120）。 至少一个或多个突起芯（130）形成在凸块的上侧上，并且由具有热固性或热塑性的聚合物材料制成。 突出芯的宽度为1〜10μm。 金属层（150）形成在突出的芯部和凸块的上侧。 金属层与衬底或另一半导体器件的电极接触。
-
公开(公告)号：KR101211753B1
公开(公告)日：2012-12-12
申请号：KR1020110071193
申请日：2011-07-18
Applicant: 한국과학기술원
CPC classification number: H01L24/29 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/75 , H01L24/81 , H01L24/83 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/73204 , H01L2224/7525 , H01L2224/81191 , H01L2224/81192 , H01L2224/83192 , H01L2224/83222 , H01L2224/83851 , H01L2224/92125 , H01L2924/01029 , H01L2924/07802 , H01L2924/07811 , H01L2924/10253 , H01L2924/15788 , H05K3/32 , H05K2201/10674 , H05K2203/102 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: PURPOSE: A method and apparatus for connecting electronic parts using a high frequency electromagnetic field are provided to heat a specific component which is contained in an interposer and a polymeric adhesive by applying a high frequency to an adhesive included in an electronic component to heat the adhesive. CONSTITUTION: An adhesive to be used in adhesion is arranged in an electronic component. The adhesive is heated using an applied high frequency. The applied high frequency simultaneously contacts a microwave electrode. The applied high frequency heats an interposer layer. The interposer layer includes one or more which are selected from components having a chemical dipole, metal, and a ferromagnetic material. [Reference numerals] (AA) Component alignment; (BB) Applying a high frequency or applying/pressurizing the high frequency
Abstract translation: 目的：提供一种使用高频电磁场连接电子部件的方法和装置，用于通过向包含在电子部件中的粘合剂施加高频加热粘合剂中的包含在插入件和聚合物粘合剂中的特定部件以加热粘合剂 。 构成：用于粘合的粘合剂被布置在电子部件中。 使用高频率加热粘合剂。 所施加的高频同时接触微波电极。 所施加的高频加热中介层。 插入层包括选自具有化学偶极子，金属和铁磁材料的组分中的一种或多种。 （附图标记）（AA）部件对准; （BB）施加高频或施加/加压高频
-
公开(公告)号：KR1020120062218A
公开(公告)日：2012-06-14
申请号：KR1020100123380
申请日：2010-12-06
Applicant: 한국과학기술원
IPC: C09J133/14 , C09J125/14 , H01L21/301 , H01L21/58
CPC classification number: C09J4/00 , C09J5/06 , C09J9/00 , C09J11/06 , C09J11/08 , C09J125/08 , C09J133/04 , H01L21/30 , H01L21/50
Abstract: PURPOSE: An adhesive composition and a preparation method of wafer level package using the composition are provided to reduce processing steps of manufacturing wafer level package. CONSTITUTION: An adhesive composition comprises a compound of chemical formula 1, a compound of chemical formula 2, or a mixture thereof. A manufacturing method of a wafer level package of comprises the following steps: spreading the wafer adhesive composition on wafer; forming a pattern by exposing the adhesive composition; dicing the wafer to individual chips; and bonding the individual chips on the circuit board by thermosetting.
Abstract translation: 目的：提供使用该组合物的晶片级封装的粘合剂组合物和制备方法，以减少制造晶片级封装的加工步骤。 构成：粘合剂组合物包含化学式1的化合物，化学式2的化合物或其混合物。 晶片级封装的制造方法包括以下步骤：将晶片粘合剂组合物铺展在晶片上; 通过暴露粘合剂组合物形成图案; 将晶片切割成单个芯片; 并通过热固性将各个芯片接合在电路板上。
-
Patent Agency Ranking
-
公开(公告)号：KR101340043B1
公开(公告)日：2013-12-10
申请号：KR1020110073757
申请日：2011-07-25
Applicant: 한국과학기술원
IPC: G06F3/041
Abstract: 본 발명은 터치 스크린 패널의 배선 구조 및 터치 스크린 패널의 배선 형성 방법에 관한 것으로서, 보다 구체적으로는 베젤 부분 아래에 은 페이스트 배선을 사용하지 않고 전면에 ITO 또는 전도성 고분자와 같은 투명 전극을 이용하여 3차원 배선을 하는 구조를 제공하여, 베젤 부분의 최소화 및 제거가 가능한 터치 스크린 패널의 배선 구조 및 터치 스크린 패널의 배선 형성 방법에 관한 것이다.
-
公开(公告)号：KR101328465B1
公开(公告)日：2013-11-14
申请号：KR1020110135648
申请日：2011-12-15
Applicant: 한국과학기술원
IPC: C09J201/00 , C09J11/00 , H05K3/32
Abstract: 라디칼 트랩 성분을 함유하는 전자부품 접속용 접착조성물이 제공된다.
본 발명에 따른 전자부품 접속용 접착조성물은 열가소성 수지, 열경화성 수지 및 경화제를 포함하는 전자부품 접속용 접착조성물로, 상기 경화제는 상기 열경화성 수지의 경화를 개시하기 위한 라디칼을 발생시키며, 상기 조성물은 상기 라디칼을 소모시키기 위한 라디칼 트랩 성분을 더 포함하는 것을 특징으로 하며, 본 발명에 따른 전자부품 접속용 접착조성물은 라디칼에 의하여 중합되는 열경화성 수지와 라디칼 트랩성분을 동시에 갖는다. 상기 첨가되는 라디칼 트랩 성분은 보관 도중 발생하는 라디칼과 결합하여, 라디칼을 소모시키나, 열접착 과정에서 다량 발생하는 라디칼은 전량 소모시키기 어려운 수준으로 첨가된다. 이에 따라, 열접착 공정 온도 미만에서는 접착조성물의 경화가 진행되지 않으므로, 접착조성물의 안정된 보관이 가능하다. 반면, 접착 공정이 진행되는 온도에서는 상기 접착조성물 내에서 발생하는 라디칼에 의하여 경화가 진행되어, 전자부품을 효과적으로 접속시킬 수 있으므로, 저온의 접착공정이 가능하다.-
公开(公告)号：KR1020120119264A
公开(公告)日：2012-10-31
申请号：KR1020110037073
申请日：2011-04-21
Applicant: 한국과학기술원
CPC classification number: H01L24/05
Abstract: PURPOSE: A chip laminating method, a chip assembly laminated by the same, and a chip manufacturing method for the same are provided to electrically connect a chip pad exposed on a side of a chip in a simple process such as thermo-compression bonding. CONSTITUTION: A chip laminating structure of a chip(100)-first insulating layer(310)-chip is formed. A second insulating layer(320) is laminated on a side of the chip laminating structure. A conductive connecting member(340) is compressed inside the second insulating layer. One or more bumps(330) is formed in the conductive connecting member. A side of a chip pad(110) is exposed in the chip laminating structure. The bump is contacted with the chip pad.
Abstract translation: 目的：提供一种芯片层叠方法，由其层叠的芯片组装体及其芯片制造方法，以热压接等简单工艺将暴露于芯片侧的芯片焊盘电连接。 构成：形成芯片（100） - 第一绝缘层（310）芯片的芯片层叠结构。 第二绝缘层（320）层压在芯片层压结构的一侧。 导电连接构件（340）在第二绝缘层内被压缩。 一个或多个凸起（330）形成在导电连接构件中。 在芯片层叠结构中，芯片焊盘（110）的一侧露出。 凸块与芯片焊盘接触。
-
公开(公告)号：KR100838647B1
公开(公告)日：2008-06-16
申请号：KR1020070073637
申请日：2007-07-23
Applicant: 한국과학기술원
IPC: H01L21/60
CPC classification number: H01L21/563 , H01L24/29 , H01L24/83 , H01L2224/05571 , H01L2224/05573 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/274 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83191 , H01L2224/83203 , H01L2224/83205 , H01L2224/83851 , H01L2224/83856 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/07811 , H01L2924/14 , H01L2924/00 , H01L2224/05599
Abstract: A method for fabricating a wafer-level flip chip package is provided to suppress shadow effects by using ACA(Anisotropic Conductive Adhesives) for easily adjusting coating thickness and NCA(Non-Conductive Adhesives), for achieving high selectivity in electrical connections while stabilizing a bonding process. A method for fabricating a wafer-level flip chip package comprises the steps of: forming a non-conductive layer(115) by coating and drying non-conductive mixture solution containing insulating polymer resin, hardener, and organic solvent onto a wafer(100) on which a non-solder bump(113) is formed; forming an anisotropic conductive layer(116) by coating and drying conductive mixture solution containing insulating polymer resin, hardener, organic solvent, and conductive materials onto the non-conductive layer; dicing the wafer coated with the non-conductive layer and anisotropic conductive layer to form individual semiconductor chips(200); and subjecting the individual semiconductor chip to a flip-chip bonding in alignment with an electrode of a substrate.
Abstract translation: 提供了一种制造晶片级倒装芯片封装的方法，以通过使用ACA（各向异性导电粘合剂）来容易地调节涂层厚度和NCA（非导电粘合剂）来抑制阴影效应，从而在稳定接合的同时实现电连接的高选择性 处理。 一种制造晶片级倒装芯片封装的方法，包括以下步骤：通过将含有绝缘聚合物树脂，硬化剂和有机溶剂的非导电混合溶液涂布并干燥到晶片（100）上而形成非导电层（115） 在其上形成非焊料凸块（113）; 通过将包含绝缘聚合物树脂，固化剂，有机溶剂和导电材料的导电混合物溶液涂布并干燥到非导电层上，形成各向异性导电层（116） 对涂覆有非导电层和各向异性导电层的晶片进行切割以形成单独的半导体芯片（200）; 以及对单个半导体芯片进行与衬底的电极对准的倒装芯片接合。
-
-
-
-
-
-
-
Search Results
28
records
(took 0.022 seconds)
