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公开(公告)号：KR1020080088189A
公开(公告)日：2008-10-02
申请号：KR1020070030773
申请日：2007-03-29
Applicant: 한국과학기술원
IPC: H03K3/356
CPC classification number: H03K3/35625 , H03K3/0372 , H03K3/0375
Abstract: An asymmetric flip-flop for reducing a leakage current is provided to reduce a leakage current by selectively increasing a gate length of transistor as a leakage source based on an input signal, an output signal and a pulse signal. An asymmetric flip-flop for reducing a leakage current includes a master terminal(210), and a slave terminal(260). The master terminal latches input data when a clock signal is a first level. The slave terminal receives and outputs the input data latched to the master terminal when the clock signal is a second level. The master terminal includes a first group of inverters(220,230,240,250). The inverters selectively have transistors with a gate-length bias in response to the input data value. The slave terminal has a second group of inverters(270,280,290). The inverters selectively have transistors with a gate-length bias in response to the output value.
Abstract translation: 提供了用于减小漏电流的非对称触发器，以便通过基于输入信号，输出信号和脉冲信号选择性地增加作为泄漏源的晶体管的栅极长度来减小泄漏电流。 用于减小漏电流的非对称触发器包括主终端（210）和从终端（260）。 当时钟信号为第一级时，主机终端锁存输入数据。 当时钟信号为第二电平时，从机终端接收并输出锁存到主终端的输入数据。 主终端包括第一组逆变器（220,230,240,250）。 反相器选择性地具有响应于输入数据值的具有栅极长度偏置的晶体管。 从属终端具有第二组逆变器（270,280,290）。 反相器选择性地具有响应于输出值的具有栅极长度偏置的晶体管。
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公开(公告)号：KR100857826B1
公开(公告)日：2008-09-10
申请号：KR1020070037863
申请日：2007-04-18
Applicant: 한국과학기술원
IPC: G11C5/14
CPC classification number: H03K19/0016 , H03K17/302 , H03K19/0185
Abstract: A power network circuit adopting zigzag power gating and a semiconductor device including the same are provided to be used easily in implementing semi-custom scheme on the basis of a conventional standard cell as having low power consumption. At least one pair of first rails(1000) comprises a power supply voltage line(1200) supplying a power supply voltage and a virtual base voltage line(1300) connected to a base voltage line of another rail pair through a first power gating circuit(1100). At least one pair of second rails(2000) comprises a virtual power supply voltage line(2200) connected to a power supply voltage line of another adjacent rail pair through a second power gating circuit(2100) and a base voltage line(2300) supplying a base voltage. The first power gating circuit is a NMOS(N-channel Metal -Oxide Semiconductor) transistor switching the connection of the base voltage line and the virtual base voltage line of the adjacent rail pair, in response to an inversion signal of a sleep mode control signal.
Abstract translation: 提供采用锯齿形电源门控的电力网络电路和包括该电源门极的半导体器件，以便在以往的标准电池的基础上实现半定制方案，因为具有低功耗。 至少一对第一轨道（1000）包括供应电源电压的电源电压线（1200）和连接到另一个轨道对的基极电压线的虚拟基极电压线（1300），通过第一电源门控电路 1100）。 至少一对第二导轨（2000）包括通过第二电源门控电路（2100）和基极电压线（2300）连接到另一相邻导轨对的电源电压线的虚拟电源电压线（2200） 基极电压。 第一功率选通电路是NMOS（N沟道金属氧化物半导体）晶体管，其响应于睡眠模式控制信号的反相信号切换基极电压线和相邻轨道对的虚拟基极电压线的连接 。
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公开(公告)号：KR100657411B1
公开(公告)日：2006-12-14
申请号：KR1020050084265
申请日：2005-09-09
Applicant: 한국과학기술원
IPC: G06F13/38
Abstract: A device for encoding/decoding a narrow bus keeping the number of transitions is provided to keep performance and the number of transitions while using the smaller number of narrow bus lines than the number of bits of raw data by serializing wide bit data when the wide bit data is sent to the narrow bus. A serializer(10) serializes n-bit raw data having an even value into n/2-bit data. A storing part(12) stores the data output from the serializer by including 'n/2' storage units. An XOR unit(14) calculates an XOR value of the data output from the serializer and the storing part by including 'n/2' XOR gates. The serializer comprises 'n/2' multiplexers and a counter for generating input of the multiplexers.
Abstract translation: 提供了一种用于对保持转换次数的窄总线进行编码/解码的设备，以在使用宽比特时通过串行化宽比特数据来保持性能和转换次数，同时使用较少数量的窄总线线路比原始数据的比特数目 数据被发送到狭窄的总线。 串行器（10）将具有偶数值的n位原始数据串行化为n / 2位数据。 存储部分（12）通过包括'n / 2'个存储单元来存储从串行器输出的数据。 XOR单元（14）通过包括'n / 2'个异或门来计算从串行器和存储部分输出的数据的XOR值。 串行器包含'n / 2'多路复用器和一个用于产生多路复用器输入的计数器。
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公开(公告)号：KR101167504B1
公开(公告)日：2012-07-20
申请号：KR1020100096846
申请日：2010-10-05
Applicant: 한국과학기술원
CPC classification number: Y02T10/7005
Abstract: 본 발명은 온라인 전기자동차(Online Electric Vehicle, OLEV)가 주행하는 도로를 세그먼트로 분할하고, 각 세그먼트의 온(on)/오프(off) 제어에 사용되는 위치센서를 차량의 속도를 고려하여 배치함으로써 전자파 저감 및 급전효율 향상을 제공하는 온라인 전기자동차용 도로 세그먼트 제어 장치 및 방법에 관한 것이다. 본 발명의 일 측면은, 전기차량이 주행하는 도로를 따라 매설되어 상기 전기차량에 전원을 공급하는 복수의 세그먼트 급전장치 및 상기 도로를 따라 배치되는 복수의 세그먼트 스위치를 포함하며, 상기 세그먼트 스위치는 상기 전기차량의 위치를 감지하여 상기 전기차량이 주행해 가는 방향에 매설된 상기 세그먼트 급전장치를 상기 전기차량의 도달 전에 미리 켜도록 하는 온라인 전기자동차용 도로 세그먼트 제어 장치를 제공한다.
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公开(公告)号：KR101134693B1
公开(公告)日：2012-04-09
申请号：KR1020090134959
申请日：2009-12-30
IPC: B60L9/00
Abstract: 본 발명은 온라인 전기자동차용 전력선 통신 방법 및 장치에 관한 것으로서, 더욱 상세하게는 도로에 설치된 전기자동차용 급전 세그먼트의 온오프 등 어떤 상황에서도 급전선의 간섭없이 전력선 통신을 가능하게 하는 온라인 전기자동차용 전력선 통신 방법 및 장치에 관한 것이다.
본 발명에 의하면, 급전 세그먼트의 온(on) 상태에서는, 급전선을 통하여 제공되는 전력에 의한 간섭신호를 제거하고, 급전 세그먼트의 오프(off) 상태에서는, 전력이 저하된 상태에서도 정상적인 통신이 가능하도록 하여, 어떤 상황에서도 급전선의 간섭없이 전력선 통신을 가능하게 한다.
전기자동차, 세그먼트, 전력선 통신, 필터-
Patent Agency Ranking
公开(公告)号：KR1020110073233A
公开(公告)日：2011-06-29
申请号：KR1020100088531
申请日：2010-09-09
Applicant: 한국과학기술원
Abstract: PURPOSE: A cruise control apparatus for the vehicles capable of maintaining the vehicular gap maintenance, and a method thereof are provided to give drivers a sense of security in case of maintaining a vehicular gap based on the driving of the vehicles, and to enhance a precision for the vehicular gap maintenance. CONSTITUTION: The cruise control apparatus for the vehicles to maintain the vehicular gap with a preceding vehicle by controlling an acceleration/deceleration part accelerating and decelerating a velocity of the vehicle includes a sensor unit(204) detecting a velocity of the vehicle and a vehicular gap with the preceding vehicle; a memory(206), in which acceleration and deceleration patterns based on velocity changes of vehicular gaps between the preceding vehicle and the vehicle are saved; a driving mode setting part(208) establishing a driving mode of the vehicle by comparing the vehicular gap detected from the sensor unit, the velocity of the vehicle and the acceleration and deceleration patterns; and a controller(210) controlling the velocity of the vehicle by controlling the acceleration/deceleration part on the driving mode. The cruise control apparatus more includes a pattern definition part(212), which collects driving information of the vehicle for a fixed time, and updates the acceleration/deceleration patterns saved in the memory. The cruise control apparatus more includes the pattern definition part, which updates the acceleration/deceleration patterns saved in the memory by using information entered by the vehicle drive. The cruise control apparatus more includes the pattern definition part, which updates the acceleration/deceleration patterns saved in the memory by using the acceleration/deceleration patterns of the preceding vehicle. The driving mode setting part compares the velocity of the vehicle, the vehicular gap, and the acceleration and deceleration patterns, and selects one of modes among cost mode, deceleration mode, acceleration mode or free racing mode. When the driving mode is a cost mode, the controller controls an acceleration/deceleration part(202) to maintain the present velocity of the vehicle.
Abstract translation: 目的：一种能够保持车辆间隙维护的车辆的巡航控制装置及其方法，其特征在于，提供一种基于驾驶车辆而保持车辆间隙的驾驶员的安全感，提高驾驶员的精度 用于车辆间隙维护。 构成：通过控制加速和减速车辆的速度的加速/减速部分，通过控制加速/减速部分来保持与前一车辆的车辆间隙的车辆巡航控制装置包括：传感器单元（204），其检测车辆的速度和车辆间隙 与前一辆车; 存储器（206），其中节省了基于前车和车辆之间的车辆间隙的速度变化的加速和减速模式; 驾驶模式设定部（208），其通过比较从所述传感器单元检测出的车辆间隙，所述车辆的速度和所述加速和减速模式来建立所述车辆的驾驶模式; 以及控制器（210），其通过在驾驶模式下控制加速/减速部分来控制车辆的速度。 巡航控制装置还具有图案定义部（212），该图案定义部（212）在一定时间内收集车辆的驾驶信息，并且更新保存在存储器中的加速/减速模式。 巡航控制装置还包括图案定义部分，其通过使用由车辆驱动器输入的信息来更新保存在存储器中的加速/减速模式。 巡航控制装置还包括图案定义部，其通过使用前方车辆的加减速图案来更新保存在存储器中的加速/减速模式。 驾驶模式设定部分比较车辆的速度，车辆间隙和加速和减速模式，并且选择成本模式，减速模式，加速模式或自由赛车模式中的一种模式。 当驾驶模式是成本模式时，控制器控制加速/减速部分（202）以保持车辆的当前速度。
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公开(公告)号：KR1020100103195A
公开(公告)日：2010-09-27
申请号：KR1020090021678
申请日：2009-03-13
IPC: H03K17/687 , H03K19/0185 , H03K19/0948
CPC classification number: H03K19/0016 , H03K19/0013
Abstract: PURPOSE: A power gating circuit and an integrated circuit including the same are provided to reduce the length of wire with respect to a mode controlling signal by utilizing a virtual power voltage as the mode controlling signal. CONSTITUTION: A logic circuit(110) performs a pre-set logic operation. The logic circuit is connected between a first power rail(VDD) and a virtual power rail(VPR). A switching unit(120) selectively connects the virtual power rail with a second power rail(VSS). A retention flip-flop(130) receives the power of the virtual power rail as a controlling signal. The retention flip-flop selectively performs a flip-flop operation or a data retention operation.
Abstract translation: 目的：提供电源门控电路和包括其的集成电路，通过利用虚拟电源电压作为模式控制信号来减少相对于模式控制信号的电线长度。 构成：逻辑电路（110）执行预置逻辑运算。 逻辑电路连接在第一电源轨（VDD）和虚拟电源轨（VPR）之间。 开关单元（120）选择性地将虚拟电源轨与第二电力轨（VSS）连接。 保持触发器（130）作为控制信号接收虚拟电源轨的电力。 保持触发器选择性地执行触发器操作或数据保持操作。
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公开(公告)号：KR1020100059184A
公开(公告)日：2010-06-04
申请号：KR1020080117863
申请日：2008-11-26
Applicant: 한국과학기술원
IPC: H03K17/28
CPC classification number: H03K5/135 , H03K3/356121 , H03K7/08
Abstract: PURPOSE: A method and an apparatus for improving the speed of pulsed latch-based digital sequential circuits are provided to effectively reduce a clock period in a digital sequential circuit using simultaneously various pulse widths and clock skew scheduling. CONSTITUTION: A net list of a gate level is input. Corresponding pulse width and clock skew are allocated in a plurality of latches which is included in the sequential circuit(S110). The latches are grouped to form a latch group. The latch group is allocated in a pulse generator(S120). A circuit arrangement process and a routing process are performed(S130). A clock tree is synthesized in order to form a clock skew(S140).
Abstract translation: 目的：提供一种用于提高基于脉冲锁存器的数字时序电路的速度的方法和装置，以有效地减少数字时序电路中的时钟周期，同时使用各种脉冲宽度和时钟偏移调度。 构成：输入门级别的净列表。 相应的脉冲宽度和时钟偏移被分配在包括在顺序电路中的多个锁存器中（S110）。 锁存器被分组以形成锁存器组。 锁存组被分配在脉冲发生器中（S120）。 执行电路布置处理和布线处理（S130）。 合成时钟树以形成时钟偏移（S140）。
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公开(公告)号：KR101612298B1
公开(公告)日：2016-04-14
申请号：KR1020090021678
申请日：2009-03-13
IPC: H03K17/687 , H03K19/0185 , H03K19/0948
CPC classification number: H03K19/0016 , H03K19/0013
Abstract: 감소된배선길이를가지는파워게이팅회로는로직회로, 스위칭소자및 리텐션플립-플롭을포함한다. 로직회로는 1 전원레일과가상전원레일사이에연결된다. 스위칭소자는모드제어신호에응답하여가상전원레일을제2 전원레일에선택적으로연결한다. 리텐션플립-플롭은가상전원레일의전압을제어신호로서수신하고, 가상전원레일의전압에응답하여플립-플롭동작또는데이터유지동작을선택적으로수행한다.
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