公开(公告)号：JP2010172014A

公开(公告)日：2010-08-05

申请号：JP2010101545

申请日：2010-04-26

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/033 ,  H04L7/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/02

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/0337

Abstract: PROBLEM TO BE SOLVED: To provide clock data recovery circuitry provided on or associated with programmable logic device circuitry. SOLUTION: A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ("LVDS"). The circuitry may be part of a larger system. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供在可编程逻辑器件电路上提供或与可编程逻辑器件电路相关联的时钟数据恢复电路。 解决方案：可编程逻辑器件（“PLD”）用可编程时钟数据恢复（“CDR”）电路进行扩充，以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以与PLD集成，或者其可以全部或部分地在单独的集成电路上。 电路可能能够进行CDR输入，CDR输出或两者。 CDR能力可以与其他非CDR信令能力组合提供，例如非CDR低电压差分信号（“LVDS”）。 电路可以是较大系统的一部分。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2006166458A

公开(公告)日：2006-06-22

申请号：JP2005352310

申请日：2005-12-06

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： SHUMARAYEV SERGEY Y ,  PATEL RAKESH

IPC: H03K19/177 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC classification number: H03K19/0016 ,  G06F17/5054 ,  G06F2217/84 ,  H01L2924/0002 ,  H03K19/00369 ,  H03K19/17732 ,  H03K19/17748 ,  H03K19/17784 ,  H03K19/17792 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To attain supply voltage and power consumption control and noise reduction and separation. SOLUTION: A programmable logic device (PLD) includes a circuit that controls a supply voltage of at least a portion of the circuitry within the PLD (such as a block, a sub-block, or a region). The circuit also filters noise within the PLD. Controlling the supply voltage allows to trade off various performance characteristics, such as speed and power consumption. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：达到电源电压和功耗控制和降噪分离。 解决方案：可编程逻辑器件（PLD）包括控制PLD内的电路的至少一部分（例如块，子块或区域）的电源电压的电路。 该电路还对PLD内的噪声进行滤波。 控制电源电压允许折衷各种性能特征，如速度和功耗。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：DE60038659D1

公开(公告)日：2008-06-05

申请号：DE60038659

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  PEDERSON BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/177 ,  H03K19/173

公开(公告)号：DE60012639T2

公开(公告)日：2005-08-04

申请号：DE60012639

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：DE60012639D1

公开(公告)日：2004-09-09

申请号：DE60012639

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：JP2013179659A

公开(公告)日：2013-09-09

申请号：JP2013095012

申请日：2013-04-30

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/033 ,  H04L7/04 ,  G11C7/22 ,  H03K5/00 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/183 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/02

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/0337

Abstract: PROBLEM TO BE SOLVED: To provide a clock data recover circuit mounted on a programmable logic device or provided by being coupled to the programmable logic device.SOLUTION: A programmable logic device ("PLD") is equipped with a programmable clock data recovery ("CDR") circuit to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuit may be built in the PLD, or it may be wholly or partly on a separate integrated circuit. The circuit may be capable of CDR input, CDR output, or both. A CDR function may be provided in combination with other non-CDR signaling function such as non-CDR low voltage differential signaling ("LVDS"). The circuit may be part of a large system.

Abstract translation: 要解决的问题：提供安装在可编程逻辑器件上或通过耦合到可编程逻辑器件提供的时钟数据恢复电路。解决方案：可编程逻辑器件（“PLD”）配备有可编程时钟数据恢复（“ CDR“）电路以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以内置在PLD中，或者它可以全部或部分地在单独的集成电路上。 该电路可能能够进行CDR输入，CDR输出或两者兼容。 CDR功能可以与诸如非CDR低电压差分信令（“LVDS”）的其它非CDR信令功能组合提供。 该电路可能是大系统的一部分。

公开(公告)号：JP2007159110A

公开(公告)日：2007-06-21

申请号：JP2006303328

申请日：2006-11-08

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： SHUMARAYEV SERGEY Y ,  PATEL RAKESH

IPC: H03K19/173 ,  H01L21/822 ,  H01L27/04 ,  H03L7/08 ,  H04L7/033

CPC classification number: H03K19/17744 ,  H03L7/0995

Abstract: PROBLEM TO BE SOLVED: To provide an FPGA transceiver capable of operating over extremely wide frequency ranges. SOLUTION: A field-programmable gate array (FPGA) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first PLL may not be adequate to meet some possible needs. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供能够在极宽频率范围内工作的FPGA收发器。 解决方案：现场可编程门阵列（FPGA）可以包括数据接收器和/或发射器电路，其适于以宽范围的任何频率或数据速率接收和/或发送数据 可能的频率或数据速率。 可能需要锁相环（PLL）电路来操作这种接收器和/或发射器电路。 为了在宽频率范围内的令人满意的操作，提供了多个PLL电路。 这些PLL电路中的一个可能能够在整个频率范围内运行，可能在该范围的某些部分中具有比该范围的其他部分更好的抖动性能。 可以提供一个或多个其他PLL电路，其集中在宽范围的特定部分上，特别是在第一PLL的抖动性能不足以满足一些可能需要的情况下。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007037133A

公开(公告)日：2007-02-08

申请号：JP2006201042

申请日：2006-07-24

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： SHUMARAYEV SERGEY YURYEVICH ,  PATEL RAKESH

IPC: H04L25/03 ,  H04L25/02

CPC classification number: G06F13/4086 ,  H03K5/1565 ,  H04L25/0274 ,  H04L25/0286 ,  H04L25/0292

Abstract: PROBLEM TO BE SOLVED: To provide a programmable duty cycle adjustment circuitry suitable for correcting duty-cycle distortions for a data signal caused by a transmission medium.
SOLUTION: The programmable duty cycle adjustment circuitry (306a, 306b; 404a, 404b) can be provided to correct duty cycle distortion in serial data transmission systems. The duty cycle adjustment can be executed prior to transmitting data signals via the transmission medium (104). The duty cycle adjustment can also be executed when data signals are received from the transmission medium. The programmable duty cycle adjustment circuitry can be configured so as to adjust the rising and falling of the data signals. The programmable duty cycle adjustment circuitry can also be configured so as to adjust the common mode level of the data signals. The amount of the duty cycle adjustment can be determined by end-users or via negative feedback.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种可编程占空比调整电路，其适用于校正由传输介质引起的数据信号的占空比失真。 解决方案：可以提供可编程占空比调整电路（306a，306b; 404a，404b）以校正串行数据传输系统中的占空比失真。 可以在通过传输介质（104）发送数据信号之前执行占空比调整。 当从传输介质接收到数据信号时，也可以执行占空比调整。 可编程占空比调整电路可以配置为调整数据信号的上升和下降。 可编程占空比调整电路也可以配置成调整数据信号的共模电平。 占空比调整的量可以由最终用户或负反馈来确定。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007028619A

公开(公告)日：2007-02-01

申请号：JP2006192210

申请日：2006-07-12

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： ASADUZZAMAN KAZI ,  SHUMARAYEV SERGEY Y ,  TRAN THUNGOC M ,  WONG WILSON ,  PATEL RAKESH

IPC: H03K19/0175 ,  H03K5/12 ,  H03K17/687

CPC classification number: H03K17/164

Abstract: PROBLEM TO BE SOLVED: To variably control a slew rate in a transmitter to be used for data transfer employing variable slew rate or various transmission protocols.
SOLUTION: A transmitter driver circuit having a variable slew rate provided by the present invention comprises a pre-driver circuit for generating a driver input signal with a variable slew rate and a driver circuit for receiving a slew rate controlled signal from the pre-driver circuit. The pre-driver circuit comprises a plurality of pre-driver stages each selectively operable to drive a pre-driver output signal related to a signal received at an input and a control circuit which responds to at least one slew rate control signal, the control circuit operates to selectively enable the pre-driver stages and to change a pre-driver output signal slew rate, and the driver circuit generates a driver output signal with a slew rate related to a slew rate of the pre-driver output signal.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：可变地控制用于使用可变转换速率或各种传输协议的数据传输的发射机中的压摆率。 解决方案：由本发明提供的具有可变转换速率的发射器驱动电路包括用于产生具有可变转换速率的驱动器输入信号的预驱动器电路和用于从预先接收压摆率控制信号的驱动电路 驱动电路。 预驱动器电路包括多个预驱动器级，每个预驱动器级可选择性地操作以驱动与在输入处接收到的信号相关的预驱动器输出信号和响应于至少一个压摆率控制信号的控制电路，控制电路 操作以选择性地启用预驱动器级并改变预驱动器输出信号转换速率，并且驱动器电路产生具有与预驱动器输出信号的转换速率相关的转换速率的驱动器输出信号。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006246534A

公开(公告)日：2006-09-14

申请号：JP2006146010

申请日：2006-05-25

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/177 ,  H01L21/82 ,  H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide an interconnection resource for applying to a programmable logic device for increasing the operating speed of a programmable logic array integrated circuit device. SOLUTION: A programmable logic integrated circuit device (10) has a plurality of programmable logic regions (20), disposed on the device with a plurality of intersecting the rows and columns of such regions. Interconnection resources for making programmable interconnections to, from and/or between the regions (e.g., interconnecting conductors or the like) are provided on the device. At least some of these interconnection resources are constituted of two forms, that are architecturally similar but that have markedly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what is called a "normal signal speed", while the smaller of the portions (200b, 210b, 230b) has a significantly higher signal speed. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于应用于可编程逻辑器件的互连资源，以提高可编程逻辑阵列集成电路器件的工作速度。 解决方案：可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域（20）设置在多个与这些区域的行和列相交的装置上。 用于在区域之间（或连接导体等）进行可编程互连的互连资源设置在该设备上。 这些互连资源中的至少一些由架构上相似但具有明显不同的信号传播速度特性的两种形式构成。 例如，这种双形互连资源（200a，210a，230a）的主要或较大部分可以具有所谓的“正常信号速度”，而较小的部分（200b，210b，230b）具有显着的 信号速度更高。 版权所有（C）2006，JPO＆NCIPI