公开(公告)号：WO0052825A9

公开(公告)日：2001-11-29

申请号：PCT/US0005488

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

公开(公告)号：WO0052826A2

公开(公告)日：2000-09-08

申请号：PCT/US0005628

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  PEDERSON BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Abstract translation: 可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

公开(公告)号：GB2306728B

公开(公告)日：2000-02-16

申请号：GB9621063

申请日：1996-10-09

Applicant: ALTERA CORP

Inventor： KARCHMER DAVID ,  REDMAN SCOTT D ,  CHEN JEFFREY ,  SCHLEICHER JAMES

IPC: G06F17/50

Abstract: The design of logic for implementation in programmable logic array integrated circuit devices is facilitated by allowing various characteristics of modules in the logic design to be parameterized. Specific values for a parameter can be "inherited" by a logic module from other logic higher in the hierarchy of the logic design. Default values for parameters can also be provided. The user can design his or her own parameterized modules, and logic designs can be recursive, meaning that a logic module can make use of other instances of itself.

公开(公告)号：DE60038659D1

公开(公告)日：2008-06-05

申请号：DE60038659

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  PEDERSON BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/177 ,  H03K19/173

公开(公告)号：DE60012639T2

公开(公告)日：2005-08-04

申请号：DE60012639

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：DE60012639D1

公开(公告)日：2004-09-09

申请号：DE60012639

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：DE60038659T2

公开(公告)日：2009-06-18

申请号：DE60038659

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  PEDERSON BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/177 ,  H03K19/173

公开(公告)号：DE69933525D1

公开(公告)日：2006-11-23

申请号：DE69933525

申请日：1999-11-15

Applicant: ALTERA CORP

Inventor： JEFFERSON DAVID E ,  LEE ANDY L ,  LANE CHRISTOPHER F ,  MCCLINTOCK CAMERON ,  MEJIA MANUEL ,  CLIFF RICHARD G ,  SCHLEICHER JAMES ,  PEDERSON BRUCE B ,  REDDY SRINIVAS T

IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

Abstract: A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

公开(公告)号：JP2006287964A

公开(公告)日：2006-10-19

申请号：JP2006146009

申请日：2006-05-25

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/177 ,  H01L21/82 ,  H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide interconnection resources to be applied to a programmable logic device for accelerating an operating speed of a programmable logic array integrated circuit. SOLUTION: A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors) are provided for making programmable interconnection to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路的工作速度。 解决方案：可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 互连资源（例如，互连导体）被提供用于对区域之间进行可编程的互连。 这些互连资源中的至少一些以架构上相似但具有显着不同的信号传播速度特性的两种形式提供。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2009065694A

公开(公告)日：2009-03-26

申请号：JP2008270378

申请日：2008-10-20

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/173 ,  H01L21/82 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide interconnection resources applied to programmable logic devices for accelerating an operating speed of a programmable logic array integrated circuit device. SOLUTION: A programmable logic integrated circuit (10) has a plurality of regions of programmable logic (20) disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, etc.) are provided for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms having architecturally similar but significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路器件的工作速度。 解决方案：可编程逻辑集成电路（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域设置在该区域的多个相交行和列的多个设备上。 提供互连资源（例如，互连导体等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以具有架构上相似但显着不同的信号传播速度特性的两种形式提供。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 版权所有（C）2009，JPO＆INPIT