公开(公告)号：JP2012130047A

公开(公告)日：2012-07-05

申请号：JP2012022868

申请日：2012-02-06

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： MAANGAT SIMARDEEP ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  TU NGOC TRAN

IPC: H04B3/04 ,  H04L25/02 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04L25/03019

Abstract: PROBLEM TO BE SOLVED: To provide an equalization circuit for appropriately compensating for attenuation caused by transmission media.SOLUTION: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. An equalization circuit (106) includes a plurality of stages (202) arranged in series to allow frequency responses of the stages (202) to be integrated together. Each stage (202) is programmable to insert a zero, thus causing the frequency response of the stage (202) to be increased in magnitude by 20 dB/decade. The frequency location of zero is also programmable to allow each stage (202) to contribute to a certain amount of a gain for a specific frequency. Each stage (202) is also programmable to determine the location of a pole for the reduction of high frequency noise and cross-talk cancellation.

Abstract translation: 要解决的问题：提供用于适当地补偿由传输介质引起的衰减的均衡电路。 解决方案：通过传输介质传输的数据信号受到传输介质所造成的衰减。 均衡电路（106）包括串联布置的多个级（202），以允许级（202）的频率响应被集成在一起。 每个级（202）可编程为插入零，从而使得级（202）的频率响应在幅度上增加20dB /十倍。 零的频率位置也是可编程的，以允许每个级（202）为特定频率贡献一定量的增益。 每个级（202）也是可编程的，以确定用于降低高频噪声和串扰消除的极点的位置。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2007028625A

公开(公告)日：2007-02-01

申请号：JP2006193262

申请日：2006-07-13

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： MAANGAT SIMARDEEP ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  TRAN THUNGOC

IPC: H04B3/04 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04L25/03019

Abstract: PROBLEM TO BE SOLVED: To provide an equalization circuit for appropriately compensating for attenuation caused by transmission media.
SOLUTION: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry (106) may include a plurality of stages (202) arranged in series to allow frequency responses of the stages (202) to be aggregated together. Each stage (202) may be programmable to insert a zero, thus causing the frequency response of the stage (202) to be increased in magnitude by 20 dB/decade. The frequency location of zero may also be programmable to allow each stage (202) to contribute to a certain amount of a gain for a specific frequency. Each stage (202) may also be programmable to determine the location of a pole for the reduction of high frequency noise and cross-talk cancellation.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于适当地补偿由传输介质引起的衰减的均衡电路。 解决方案：通过传输介质传输的数据信号受到传输介质所造成的衰减。 均衡电路（106）可以包括串联布置的多个级（202），以允许级（202）的频率响应聚合在一起。 每个级（202）可以是可编程的以插入零，从而使得级（202）的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级（202）为特定频率贡献一定量的增益。 每个级（202）也可以被编程以确定用于降低高频噪声和串扰消除的极点的位置。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006203908A

公开(公告)日：2006-08-03

申请号：JP2006013254

申请日：2006-01-20

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： SHUMARAYEV SERGEY Y ,  PATEL RAKESH H ,  WONG WILSON ,  HOANG TIM T

IPC: H03L7/087 ,  G06F1/06 ,  H03L7/08 ,  H03L7/081 ,  H04L7/033

CPC classification number: H03L7/0998 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To provide a technology for generating a restoring clock signal using a multi-mode clock data recovery (CDR) circuit meeting requirements of flexible ranged operating frequency F and continuous identical codes CID. SOLUTION: In first mode, a controlled oscillator provides the restoring clock signal, and in second mode, a phase interpolator provides the restoring clock signal. The multi-mode CDR circuit operates in the first mode when (CID/F) is less than a time tolerance, or operates in the second mode when the (CID/F) is greater than the time tolerance. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种使用满足柔性范围工作频率F和连续相同代码CID的要求的多模式时钟数据恢复（CDR）电路来产生恢复时钟信号的技术。 解决方案：在第一模式中，受控振荡器提供恢复时钟信号，而在第二模式中，相位内插器提供恢复时钟信号。 当（CID / F）小于时间容限时，多模式CDR电路在第一模式下工作，或者当（CID / F）大于时间容差时，多模式CDR电路在第一模式下工作。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：EP2695303A4

公开(公告)日：2014-10-08

申请号：EP12767589

申请日：2012-03-27

Applicant: ALTERA CORP

Inventor： DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  HOANG TIM TRI ,  KE YANJING

IPC: H04B1/04 ,  H03K3/017 ,  H03L7/00

CPC classification number: H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

公开(公告)号：JP2009147947A

公开(公告)日：2009-07-02

申请号：JP2008320309

申请日：2008-12-16

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： DING WEIQI ,  LIU MENGCHI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H04L25/03 ,  H04B3/04 ,  H04L27/01

CPC classification number: H04L25/03878 ,  H04L7/0054

Abstract: PROBLEM TO BE SOLVED: To provide a data conversion process which can convert a serial data format to a parallel data format successfully and efficiently, and also to provide a data conversion process in the opposite direction. SOLUTION: The receiver circuitry for receiving high-speed serial data signals having serial bit rates in the range of about 10 Gbps includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Each of the stages has variable parameters of a DC gain, and a pole and/or zero whose location is variable with respect to frequency. The parameters of the DC gain at each stage and the locations of the pole and/or zero are variable by programs. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供可以成功且有效地将串行数据格式转换为并行数据格式的数据转换处理，并且还提供相反方向的数据转换处理。 解决方案：用于接收具有大约10Gbps范围内的串行比特率的高速串行数据信号的接收机电路包括仅具有两个串联连接级的两级连续时间线性均衡器。 每个级具有DC增益的可变参数，以及位置相对于频率可变的极点和/或零点。 每个阶段的直流增益参数和极点和/或零点的位置都可以通过程序来实现。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008236738A

公开(公告)日：2008-10-02

申请号：JP2008037812

申请日：2008-02-19

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： CHAN ALLEN ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03K19/173

CPC classification number: G06F13/385 ,  H03K19/177 ,  H03K19/17744 ,  H04L5/1446

Abstract: PROBLEM TO BE SOLVED: To provide a rate negotiation independent of a protocol in use in a PLD receiver-transmitter.
SOLUTION: A method for determining a data rate in a serial interface channel for a programmable logic device operating at a clock rate includes; monitoring the channel for occurrence of a single bit transition, and concluding that the data rate is virtually a multiple of the clock rate based on detection of a plurality of single bit transitions in a predefined duration.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供与PLD接收机 - 发射机中使用的协议无关的速率协商。 解决方案：用于确定以时钟速率工作的可编程逻辑器件的串行接口通道中的数据速率的方法包括： 监视通道以发生单个位转换，并且基于在预定义的持续时间内检测到多个单个位转换，得出数据速率实际上是时钟速率的倍数。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007174637A

公开(公告)日：2007-07-05

申请号：JP2006318128

申请日：2006-11-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  RAKESH PATEL H ,  SHUMARAYEV SERGEY ,  LAI TIN H

IPC: H04B3/06

CPC classification number: H04B7/005 ,  H04L25/03006 ,  H04L25/061

Abstract: PROBLEM TO BE SOLVED: To provide technologies for adjusting a signal received from a communication path.
SOLUTION: The systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency component of the received signal, a signal normalization block that provides a normalized signal amplitude and a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but does not control for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. Thus, the controlled adjustment for low frequency content is executed in the signal normalization block.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于调整从通信路径接收的信号的技术。 公开了用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率分量中的至少一些的均衡块，提供归一化信号幅度和归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频的均衡块中的频率调整，但不控制低频。 对于低频调整，控制块控制信号归一化块中的归一化信号幅度。 因此，在信号归一化块中执行低频内容的受控调整。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：EP2366110A4

公开(公告)日：2015-04-29

申请号：EP09824046

申请日：2009-10-26

Applicant: ALTERA CORP

Inventor： WONG WILSON ,  CHAN ALLEN ,  SHUMARAYEV SERGEY

IPC: G01R31/28 ,  G01R31/3167 ,  H03M1/12

CPC classification number: G01R31/3167

公开(公告)号：JP2013251916A

公开(公告)日：2013-12-12

申请号：JP2013161153

申请日：2013-08-02

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： DING WEIQI ,  LIU MENGCHI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H04L25/03 ,  H04B3/04

CPC classification number: H04L25/03878 ,  H04L7/0054

Abstract: PROBLEM TO BE SOLVED: To provide preferable and efficient data conversion processes between a high-speed serial data format and a parallel data format.SOLUTION: Receiver circuitry for receiving a high-speed serial data signal having a serial bit rate in the range of about 10 Gbps includes a two-stage continuous-time linear equalizer having only two stages connected in series. Each of the stages has a DC gain parameter which is variable, and a pole and/or a zero whose locations are variable in terms of the frequency. The DC gain parameter and the pole and/or zero locations of each stage are variable by programs.

Abstract translation: 要解决的问题：提供高速串行数据格式和并行数据格式之间优选和有效的数据转换处理。解决方案：接收电路，用于接收串行比特率在大约的范围内的高速串行数据信号 10Gbps包括仅具有串联连接的两级的两级连续时间线性均衡器。 每个级具有可变的DC增益参数，以及位置在频率方面可变的极点和/或零点。 每个阶段的直流增益参数和极点和/或零点位置都可以通过程序进行变化。

公开(公告)号：JP2011103678A

公开(公告)日：2011-05-26

申请号：JP2010291281

申请日：2010-12-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04B3/04 ,  H04L25/03

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptation circuitry and method for a programmable logic device. SOLUTION: A method of controlling equalization of an incoming data signal includes: detecting two continuous bits having different values in the data signal; determining whether transition in the incoming data signal between the two bits is relatively slow or relatively fast; and increasing the equalization of the incoming data signal when the transition is relatively slow. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为可编程逻辑器件提供数字适配电路和方法。 控制输入​​数据信号的均衡的方法包括：检测数据信号中具有不同值的两个连续位; 确定两个位之间的输入数据信号中的转换是相对较慢还是相对较快; 并且当转换相对较慢时，增加输入数据信号的均衡。 版权所有（C）2011，JPO＆INPIT