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    MULTILEVEL BIPOLAR PULSER
    22.
    发明专利
    MULTILEVEL BIPOLAR PULSER 未知

    公开(公告)号：CA3018387A1

    公开(公告)日：2017-10-05

    申请号：CA3018387

    申请日：2017-03-31

    Applicant: BUTTERFLY NETWORK INC

    Inventor： CHEN KAILIANG ,  RALSTON TYLER S ,  FIFE KEITH G

    IPC: A61B8/00 ,  H01L41/00 ,  H02N2/00

    Abstract: Circuitry for ultrasound devices is described. A multilevel pulser is described, which can provide bipolar pulses of multiple levels. The multilevel pulser includes a pulsing circuit and pulser and feedback circuit. Symmetric switches are also described. The symmetric switches can be positioned as inputs to ultrasound receiving circuitry to block signals from the receiving circuitry.

    Ultrasound transducer devices and methods for fabricating ultrasound transducer devices
    27.
    发明专利
    Ultrasound transducer devices and methods for fabricating ultrasound transducer devices 未知

    公开(公告)号：AU2019231793A1

    公开(公告)日：2020-09-24

    申请号：AU2019231793

    申请日：2019-03-08

    Applicant: BUTTERFLY NETWORK INC

    Inventor： FIFE KEITH G ,  LIU JIANWEI

    IPC: B06B1/00 ,  B81B3/00 ,  B81C1/00 ,  G10K9/12 ,  G10K11/18

    Abstract: Aspects of the technology described herein relate to ultrasound transducer devices including capacitive micromachined ultrasonic transducers (CMUTs) and methods for forming CMUTs in ultrasound transducer devices. Some embodiments include forming a cavity of a CMUT by forming a first layer of insulating material on a first substrate, forming a second layer of insulating material on the first layer of insulating material, and then etching a cavity in the second insulating material. A second substrate may be bonded to the first substrate to seal the cavity. The first layer of insulating material may include, for example, aluminum oxide. The first substrate may include integrated circuitry. Some embodiments include forming through- silicon vias (TSVs) in the first substrate prior to forming the first and second insulating layers (TSV-Middle process) or subsequent to bonding the first and second substrates (TSV-Last process).

    METHODS AND APPARATUSES FOR PACKAGING AN ULTRASOUND-ON-A-CHIP
    29.
    发明专利
    METHODS AND APPARATUSES FOR PACKAGING AN ULTRASOUND-ON-A-CHIP 未知

    公开(公告)号：CA3105492A1

    公开(公告)日：2020-01-09

    申请号：CA3105492

    申请日：2019-07-03

    Applicant: BUTTERFLY NETWORK INC

    Inventor： LIU JIANWEI ,  FIFE KEITH G

    IPC: G01N29/22 ,  A61B8/00

    Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.

    ULTRASOUND APPARATUSES AND METHODS FOR FABRICATING ULTRASOUND DEVICES
    30.
    发明专利
    ULTRASOUND APPARATUSES AND METHODS FOR FABRICATING ULTRASOUND DEVICES 未知

    公开(公告)号：CA3081760A1

    公开(公告)日：2019-05-23

    申请号：CA3081760

    申请日：2018-11-15

    Applicant: BUTTERFLY NETWORK INC

    Inventor： CHEN KAILIANG ,  SANCHEZ NEVADA J ,  ALIE SUSAN A ,  RALSTON TYLER S ,  ROTHBERG JONATHAN M ,  FIFE KEITH G ,  LUTSKY JOSEPH

    IPC: A61B8/00 ,  H01L21/98 ,  H01L23/535

    Abstract: Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application- specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

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