公开(公告)号：WO2005043591A8

公开(公告)日：2005-11-03

申请号：PCT/US2004034562

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

IPC: H01L20060101 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10 ,  H01L

CPC classification number: H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract translation: 一种半导体器件和制造半导体器件的方法。 该半导体器件包括用于pFET和nFET的沟道。 SiGe层选择性地生长在pFET沟道的源极和漏极区中，并且Si：C层选择性生长在nFET沟道的源极和漏极区中。 SiGe和Si：C层匹配下面的Si层的晶格网络以产生应力分量。 在一个实施方式中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

公开(公告)号：DE602004032035D1

公开(公告)日：2011-05-12

申请号：DE602004032035

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

IPC: H01L31/0328 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

公开(公告)号：SG142307A1

公开(公告)日：2008-05-28

申请号：SG2008029332

申请日：2005-09-29

Applicant: IBM ,  TOSHIBA KK

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  OH SANG-HYUN ,  PANDA SIDDHARTHA ,  RAUSCH WERNER A ,  SATO TSUTOMU ,  UTOMO HENRY K

Abstract: STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER A field effect transistor (FET) (10) is provided which includes a gate stack (29), a pair of first spacers (32) disposed over sidewalls of the gate stack (29) and a pair of semiconductor alloy regions (39) disposed on opposite sides of and spaced a first distance from the gate stack (29). Source and drain regions (24) of the FET (10) are at least partly disposed in the semiconductor alloy regions (39); and spaced a second distance from the gate stack (29) by a corresponding spacer of the pair of first spacers (32), which may be different from the first distance. The FET (10) may also include second spacers (34) disposed on the first spacers (32), and silicide regions (40) at least partly overlying the semiconductor alloy regions (39), wherein the silicide regions (40) are spaced from the gate stack (29) by the first and second spacers (32, 34).

公开(公告)号：AT552611T

公开(公告)日：2012-04-15

申请号：AT04703076

申请日：2004-01-16

Applicant: IBM

Inventor： CHEN HUAJIE ,  BEDELL STEPHEN ,  SADANA DEVENDRA ,  MOCUTA DAN

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/762 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

Abstract: A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550° C.-700° C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH4.