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    METHOD OF FABRICATING A STRAINED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE
    1.
    发明申请
    METHOD OF FABRICATING A STRAINED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 审中-公开
    制造应变半导体绝缘体基板的方法

    公开(公告)号：WO2005055290A3

    公开(公告)日：2005-09-09

    申请号：PCT/EP2004053204

    申请日：2004-12-01

    Applicant: IBM ,  IBM UK ,  BEDELL STEPHEN ,  COHEN GUY ,  CHEN HUAJIE

    Inventor： BEDELL STEPHEN ,  COHEN GUY ,  CHEN HUAJIE

    IPC: H01L21/20 ,  H01L21/324 ,  H01L21/762

    CPC classification number: H01L21/324

    Abstract: A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate in which the strained semiconductor is a thin semiconductor layer having a thickness of less than 50 nm that is located directly atop an insulator layer of a preformed silicon-on-insulator substrate is provided. Wafer bonding is not employed in forming the SSOI substrate of the present invention.

    Abstract translation: 一种制造应变半导体绝缘体（SSOI）衬底的方法，其中应变半导体是厚度小于50nm的薄半导体层，其直接位于预成型的绝缘体上硅衬底上的绝缘体层的顶部 被提供。 在形成本发明的SSOI基板时不使用晶片接合。

    STRAINED SEMICONDUCTOR-ON-INSULATOR BY SI:C COMBINED WITH POROUS PROCESS
    2.
    发明申请
    STRAINED SEMICONDUCTOR-ON-INSULATOR BY SI:C COMBINED WITH POROUS PROCESS 审中-公开
    通过与多孔工艺组合的SI：C的应变半导体绝缘体

    公开(公告)号：WO2009056478A2

    公开(公告)日：2009-05-07

    申请号：PCT/EP2008064272

    申请日：2008-10-22

    Applicant: IBM ,  BEDELL STEPHEN ,  DE SOUZA JOEL ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA

    Inventor： BEDELL STEPHEN ,  DE SOUZA JOEL ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA

    IPC: H01L21/762

    CPC classification number: H01L21/76245 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/3167

    Abstract: A method of fabricating a strained semiconductor-on- insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.

    Abstract translation: 提供一种制造应变半导体绝缘体（SSOI）衬底的方法。 该方法包括首先提供包括衬底，衬底上的掺杂和弛豫半导体层以及掺杂和弛豫半导体层上的应变半导体层的结构。 在本发明中，掺杂和松弛的半导体层具有比衬底更低的晶格参数。 接下来，至少将掺杂和松弛的半导体层转换成掩埋多孔层，并且将包括埋入多孔层的结构退火以提供应变绝缘体上半导体衬底。 在退火过程中，将埋入的多孔层转化为掩埋氧化物层。

    WIEDERAUFLADBARE BATTERIESTAPEL
    3.
    发明专利
    WIEDERAUFLADBARE BATTERIESTAPEL 未知

    公开(公告)号：DE112018003525T5

    公开(公告)日：2020-04-16

    申请号：DE112018003525

    申请日：2018-09-11

    Applicant: IBM

    Inventor： LEE YUN SEOG ,  BEDELL STEPHEN ,  DE SOUZA JOEL PEREIRA ,  SADANA DEVENDRA

    IPC: H01M10/04

    Abstract: Es werden wiederaufladbare Batterien mit einer hohen Kapazität (d.h. mit einer Kapazität von 50 mAh/gm oder einer höheren Kapazität) und einem hohen Leistungsvermögen bereitgestellt, die einen wiederaufladbaren Batteriestapel enthalten, der eine Struktur aus einem abgeblätterten Material aufweist, die eine Schicht aus einem Kathodenmaterial umfasst, die an einem Stressormaterial angebracht ist. Das Kathodenmaterial kann ein einkristallines Material aufweisen, das frei von polymeren Bindemitteln ist. Das Stressormaterial dient als ein Kathodenstromkollektor des wiederaufladbaren Batteriesta pels.

    Back-surface field structures for multi-junction III-V photovoltaic devices
    5.
    发明专利
    Back-surface field structures for multi-junction III-V photovoltaic devices 未知

    公开(公告)号：GB2495828B

    公开(公告)日：2013-09-25

    申请号：GB201218439

    申请日：2012-10-15

    Applicant: IBM

    Inventor： SHAHRJERDI DAVOOD ,  HEKMATSHOARTABARI BAHMAN ,  BEDELL STEPHEN ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM G

    IPC: H01L31/0725

    Abstract: A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline.

    Active Matrix Inorganic Light Emitting Diode Array
    7.
    发明专利
    Active Matrix Inorganic Light Emitting Diode Array 未知

    公开(公告)号：GB2496970A

    公开(公告)日：2013-05-29

    申请号：GB201220562

    申请日：2012-11-15

    Applicant: IBM

    Inventor： HEKMATSHOARTABARI BAHMAN ,  SHAHRJERDI DAVOOD ,  BEDELL STEPHEN ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM G

    IPC: H01L27/15 ,  H01L27/12 ,  H01L33/00 ,  H01L33/62

    Abstract: A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material 804 originally grown thereupon; and bonding the removed layer of inorganic LED material 804 to an active matrix, thin film transistor (TFT) backplane array 802. Also disclosed is the active matrix light emitting diode array produced from said method. The inorganic LED material 804 may be removed from the base substrate by a method of spalling, wherein at least one or more stress layers are formed on the inorganic LED material layer, a flexible handle layer is formed on the one or more stress layers, and applying a force to the flexible handle layer so as to separate the stress layer and at least a portion of the inorganic LED material layer from the base substrate. The inorganic LED material layer 804 may be bonded to the active matrix TFT backplane array 802 by a process of cold welding. The inorganic LED material layer 804 may be patterned once bonded to the active matrix TFT backplane array 802, where a further inorganic LED material layer 804b can be bonded to the backplane array 802 to produce an array of LED elements 804a,804b, wherein the further inorganic LED material layer 804b is produced by the same method as the first inorganic LED material layer 804a.

    Controlled spalling of group III nitrides containing an embedded spall releasing plane
    8.
    发明专利
    Controlled spalling of group III nitrides containing an embedded spall releasing plane 未知

    公开(公告)号：GB2521517A

    公开(公告)日：2015-06-24

    申请号：GB201418871

    申请日：2014-10-23

    Applicant: IBM

    Inventor： BAYRAM CAN ,  SADANA DEVENDRA ,  BEDELL STEPHEN ,  OTT JOHN ,  FOGEL KEITH

    IPC: H01L31/18

    Abstract: A spall releasing plane 15 is formed in the middle of and embedded within a Group III nitride material layer 14. The spall releasing plane includes a material that has a different strain, a different structure and a different composition compared with the Group III nitride material portions and can be formed by adding impurities during the vapour deposition process. Device layer 16, stressor layer 22 and handle 24 are deposited onto the upper surface of the material layer. An edge exclusion layer 18 and adhesion layer 20 can be added above the device layer to aide in the spalling process. This method overcomes the issue of having a lattice mismatch when using Group III nitride materials, e.g. GaN, AlN, InGaN.

    METHOD FOR CONTROLLED SPALLING
    10.
    发明专利
    METHOD FOR CONTROLLED SPALLING 未知

    公开(公告)号：GB2493244A

    公开(公告)日：2013-01-30

    申请号：GB201210426

    申请日：2012-06-13

    Applicant: IBM

    Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  SADANA DEVENDRA

    IPC: H01L31/18

    Abstract: A method of controlled layer transfer is provided. The method includes providing a stressor layer 16 to a base substrate. The stressor layer has a stressor layer portion 16A located atop an upper surface (12, fig. 1) of the base substrate 10 and a self-pinning stressor layer portion 16B located adjacent each sidewall edge of the base substrate. A spalling inhibitor (20) is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion by applying a laser or chemical etch to the self-pinning stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion to control the spalling.

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