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    SPALLING FOR A SEMICONDUCTOR SUBSTRATE
    2.
    发明申请
    SPALLING FOR A SEMICONDUCTOR SUBSTRATE 审中-公开
    用于半导体衬底的分离

    公开(公告)号：WO2011106203A3

    公开(公告)日：2011-11-17

    申请号：PCT/US2011024948

    申请日：2011-02-16

    Applicant: IBM ,  BEDELL STEPHEN W ,  FOGEL KEITH E ,  LAURO PAUL A ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD

    Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  LAURO PAUL A ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD

    IPC: H01L21/304 ,  B28D5/00

    CPC classification number: H01L31/075 ,  H01L21/02002 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

    Abstract: A method for spalling a layer from an ingot of a semiconductor substrate includes forming a metal layer on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot; and removing the layer from the ingot at the fracture. A system for spalling a layer from an ingot of a semiconductor substrate includes a metal layer formed on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot, and wherein the layer is configured to be removed from the ingot at the fracture.

    Abstract translation: 一种用于从半导体衬底的晶锭剥落层的方法包括：在半导体衬底的晶块上形成金属层，其中金属层中的拉伸应力被配置为引起晶块中的断裂; 并在裂缝处从锭块中去除层。 用于从半导体衬底的晶锭剥落层的系统包括形成在半导体衬底的晶锭上的金属层，其中金属层中的拉应力被配置为引起晶块中的断裂，并且其中该层被配置 在骨折处从锭块中移出。

    SEMICONDUCTOR OPTICAL DETECTOR STRUCTURE
    3.
    发明申请
    SEMICONDUCTOR OPTICAL DETECTOR STRUCTURE 审中-公开
    半导体光学探测器结构

    公开(公告)号：WO2011005447A2

    公开(公告)日：2011-01-13

    申请号：PCT/US2010039007

    申请日：2010-06-17

    Applicant: IBM ,  DE SOUZA JOEL ,  HOVEL HAROLD ,  INNS DANIEL ,  KIM JEE ,  SADANA DEVENDRA

    Inventor： DE SOUZA JOEL ,  HOVEL HAROLD ,  INNS DANIEL ,  KIM JEE ,  SADANA DEVENDRA

    IPC: H01L31/18 ,  H01L31/068 ,  H01L31/072 ,  H01L31/078

    CPC classification number: H01L31/1872 ,  H01L31/03921 ,  H01L31/068 ,  H01L31/078 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

    Abstract: A semiconductor is disclosed with a substrate doped with a substrate doping. There is a crystalline semiconductor layer disposed on a front side of the substrate. The crystalline semiconductor layer has a layer doping. The substrate doping changes to the layer doping within a 100 angstrom transition region. In alternative embodiments, the layer doping has novel profiles. In other alternative embodiments, the substrate has a crystalline semiconductor layers disposed on each of a front and a back side of the substrate. Each of the crystalline semiconductor layers has a respective layer doping and each of these layer dopings changes to the substrate doping within a respective transition region less than 100 angstroms thick. In still other embodiments of this invention, an amorphous silicon layer is disposed on a side of the crystalline semiconductor layer opposite the substrate. The amorphous silicon layer has an amorphous doping so that a tunnel junction is formed between the doped crystalline semiconductor layer and the amorphous layer. Manufacturing these structures at below 700 degrees Centigrade enables the narrow transition regions of the structures.

    Abstract translation: 公开了一种掺杂有衬底掺杂的衬底的半导体。 在衬底的正面上设置有晶体半导体层。 晶体半导体层具有层掺杂。 衬底掺杂改变为在100埃过渡区内的层掺杂。 在替代实施例中，层掺杂具有新颖的轮廓。 在其他替代实施例中，衬底具有布置在衬底的前侧和后侧中的每一个上的晶体半导体层。 每个晶体半导体层具有相应的层掺杂并且这些层掺杂中的每一个都变为在小于100埃厚的相应过渡区域内的衬底掺杂。 在本发明的其他实施例中，非晶硅层设置在与衬底相对的晶体半导体层的一侧。 非晶硅层具有非晶掺杂，使得在掺杂的晶体半导体层和非晶层之间形成隧道结。 在700摄氏度以下制造这些结构使得结构的狭窄过渡区域成为可能。

    SINGLE-JUNCTION PHOTOVOLTAIC CELL
    4.
    发明申请
    SINGLE-JUNCTION PHOTOVOLTAIC CELL 审中-公开
    单晶光伏电池

    公开(公告)号：WO2011106204A2

    公开(公告)日：2011-09-01

    申请号：PCT/US2011024949

    申请日：2011-02-16

    Applicant: IBM ,  BEDELL STEPHEN W ,  FOGEL KEITH E ,  SOSA CORTES NORMA E ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD ,  WACASER BRENT A

    Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  SOSA CORTES NORMA E ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD ,  WACASER BRENT A

    IPC: H01L31/042 ,  H01L31/06

    CPC classification number: H01L31/0304 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

    Abstract: A method for forming a single-junction photovoltaic cell includes forming a dopant layer on a surface of a semiconductor substrate; diffusing the dopant layer into the semiconductor substrate to form a doped layer of the semiconductor substrate; forming a metal layer over the doped layer, wherein a tensile stress in the metal layer is configured to cause a fracture in the semiconductor substrate; removing a semiconductor layer from the semiconductor substrate at the fracture; and forming the single-junction photovoltaic cell using the semiconductor layer. A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.

    Abstract translation: 一种形成单结光伏电池的方法包括在半导体衬底的表面上形成掺杂剂层; 将掺杂剂层扩散到半导体衬底中以形成半导体衬底的掺杂层; 在所述掺杂层上形成金属层，其中所述金属层中的拉伸应力构造成在所述半导体衬底中引起断裂; 在断裂时从半导体衬底去除半导体层; 以及使用半导体层形成单结光伏电池。 单结光伏电池包括掺杂剂，该掺杂层包含扩散到半导体衬底中的掺杂剂; 形成在掺杂层上的图案化导电层; 半导体层，其包括位于掺杂层的与图案化导电层相对的表面上的掺杂层上的半导体衬底; 以及形成在半导体层上的欧姆接触层。

    STRAINED SEMICONDUCTOR-ON-INSULATOR BY SI:C COMBINED WITH POROUS PROCESS
    5.
    发明申请
    STRAINED SEMICONDUCTOR-ON-INSULATOR BY SI:C COMBINED WITH POROUS PROCESS 审中-公开
    通过与多孔工艺组合的SI：C的应变半导体绝缘体

    公开(公告)号：WO2009056478A2

    公开(公告)日：2009-05-07

    申请号：PCT/EP2008064272

    申请日：2008-10-22

    Applicant: IBM ,  BEDELL STEPHEN ,  DE SOUZA JOEL ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA

    Inventor： BEDELL STEPHEN ,  DE SOUZA JOEL ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA

    IPC: H01L21/762

    CPC classification number: H01L21/76245 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/3167

    Abstract: A method of fabricating a strained semiconductor-on- insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.

    Abstract translation: 提供一种制造应变半导体绝缘体（SSOI）衬底的方法。 该方法包括首先提供包括衬底，衬底上的掺杂和弛豫半导体层以及掺杂和弛豫半导体层上的应变半导体层的结构。 在本发明中，掺杂和松弛的半导体层具有比衬底更低的晶格参数。 接下来，至少将掺杂和松弛的半导体层转换成掩埋多孔层，并且将包括埋入多孔层的结构退火以提供应变绝缘体上半导体衬底。 在退火过程中，将埋入的多孔层转化为掩埋氧化物层。

    All-semiconductor Josephson junction device for qubit applications
    6.
    发明专利
    All-semiconductor Josephson junction device for qubit applications 未知

    公开(公告)号：AU2021236824A1

    公开(公告)日：2022-07-28

    申请号：AU2021236824

    申请日：2021-02-16

    Applicant: IBM

    Inventor： HOLMES STEVEN ,  SADANA DEVENDRA ,  GLUSCHENKOV OLEG

    IPC: H01L39/02 ,  H01L39/12 ,  H01L39/22 ,  H01L39/24

    Abstract: According to an embodiment of the present invention, a quantum mechanical device includes a monolithic crystalline structure. The monolithic crystalline structure includes a first region doped to provide a first superconducting region, and a second region doped to provide a second superconducting region, the second superconducting region being separated from the first superconducting region by an undoped crystalline region. The first and second superconducting regions and the undoped crystalline region form a Josephson junction.

    LITHIUMIONEN-DÜNNSCHICHTBATTERIE MIT HOHER LADEGESCHWINDIGKEIT
    7.
    发明专利
    LITHIUMIONEN-DÜNNSCHICHTBATTERIE MIT HOHER LADEGESCHWINDIGKEIT 未知

    公开(公告)号：DE112018004123T5

    公开(公告)日：2020-05-07

    申请号：DE112018004123

    申请日：2018-07-26

    Applicant: IBM

    Inventor： LEE YUN SEOG ,  SADANA DEVENDRA ,  DE SOUZA JOEL PEREIRA

    IPC: H01M10/0525

    Abstract: Es wird eine Festkörperbatterie auf Lithiumbasis mit hoher Lade- und Wiederaufladegeschwindigkeit (über 3 C) bereitgestellt, indem zwischen der Schicht des lithiierten Kathodenmaterials und der Festkörper-Elektrolytschicht auf Lithiumbasis eine Oberflächenschicht eines mit Stickstoff angereicherten lithiierten Kathodenmaterials eingefügt wird. Die Oberflächenschicht des mit Stickstoff angereicherten lithiierten Kathodenmaterials kann durch Einbringen von Stickstoff in ein lithiiertes Kathodenmaterial gebildet werden. Der Stickstoff kann während der abschließenden Stufe eines Abscheidungsverfahrens eingebracht werden, oder über ein anderes Verfahren als ein Abscheidungsverfahren, wie zum Beispiel über eine thermische Nitrierung.

    Controlled spalling of group III nitrides containing an embedded spall releasing plane
    8.
    发明专利
    Controlled spalling of group III nitrides containing an embedded spall releasing plane 未知

    公开(公告)号：GB2521517A

    公开(公告)日：2015-06-24

    申请号：GB201418871

    申请日：2014-10-23

    Applicant: IBM

    Inventor： BAYRAM CAN ,  SADANA DEVENDRA ,  BEDELL STEPHEN ,  OTT JOHN ,  FOGEL KEITH

    IPC: H01L31/18

    Abstract: A spall releasing plane 15 is formed in the middle of and embedded within a Group III nitride material layer 14. The spall releasing plane includes a material that has a different strain, a different structure and a different composition compared with the Group III nitride material portions and can be formed by adding impurities during the vapour deposition process. Device layer 16, stressor layer 22 and handle 24 are deposited onto the upper surface of the material layer. An edge exclusion layer 18 and adhesion layer 20 can be added above the device layer to aide in the spalling process. This method overcomes the issue of having a lattice mismatch when using Group III nitride materials, e.g. GaN, AlN, InGaN.

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