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    DATA PROCESSING APPARATUS
    24.
    发明专利
    DATA PROCESSING APPARATUS 未知

    公开(公告)号：HK88292A

    公开(公告)日：1992-11-20

    申请号：HK88292

    申请日：1992-11-12

    Applicant: IBM

    Inventor： DAY MICHAEL NORMAN

    IPC: G06F1/04 ,  G06F1/32 ,  G06F15/02 ,  G06F1/00

    Abstract: An apparatus and method are provided for disabling the clocking of a processor in a battery operated computer during non-processing times. The clocking is disabled at the conclusion of a processing operation. The clocking can then be re-enabled using interrupts from any one of a plurality of sources, such as an I/O device or a direct memory access. Application programs and operating system programs running on the system can specify the stopping of the system clock and the central processor until a specified event which had been requested occurs, or until an optional time-out period has expired. In this situation, the event is defined as one that results in either a system interrupt from an I/O device or from a direct memory access operation. The stopping of the system clock is a two part operation wherein in the first part the stopping mechanism is first armed. If an interrupt is received subsequent to arming, then it will be processed and the arming mechanism will be reset. However, if an interrupt does not occur after arming within a specified time period, then the system clock will be stopped.

    SYSTEM AND METHOD FOR VIRTUALIZATION OF PROCESSOR RESOURCES
    26.
    发明专利
    SYSTEM AND METHOD FOR VIRTUALIZATION OF PROCESSOR RESOURCES 未知

    公开(公告)号：CA2577865C

    公开(公告)日：2011-09-27

    申请号：CA2577865

    申请日：2005-08-24

    Applicant: IBM

    Inventor： AGUILAR MAXIMINO JR ,  DAY MICHAEL NORMAN ,  NUTTER MARK RICHARD ,  XENIDIS JAMES

    IPC: G06F12/10 ,  G06F12/02

    Abstract: In a system and method for virtualization of processor resources, a thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a "soft" copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.

    27.
    发明专利
    未知

    公开(公告)号：BRPI0515920A2

    公开(公告)日：2009-08-04

    申请号：BRPI0515920

    申请日：2005-08-24

    Applicant: IBM

    Inventor： AGUILAR MAXIMINO JR ,  DAY MICHAEL NORMAN ,  NUTTER MARK RICHARD ,  XENIDIS JAMES

    IPC: G06F12/10 ,  G06F12/02

    Abstract: A system and method for virtualization of processor resources is presented. A thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a "soft" copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.

    29.
    发明专利
    未知

    公开(公告)号：DE602005008747D1

    公开(公告)日：2008-09-18

    申请号：DE602005008747

    申请日：2005-07-18

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

    Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG ,  YAMAZAKI TAKESHI

    IPC: G06F13/28 ,  G06F9/46

    Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

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