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公开(公告)号：DE69638095D1
公开(公告)日：2010-01-21
申请号：DE69638095
申请日：1996-07-09
Applicant: IBM
Inventor： COLMANT MICHEL , ENGBERSEN ANTONIUS P , HEDDES MARCO , VAN WEERT MARINUS J
IPC: H04Q3/00 , H04Q11/04 , H04L12/54 , H04L12/70 , H04L12/933
Abstract: PCT No. PCT/IB96/00658 Sec. 371 Date Apr. 13, 1998 Sec. 102(e) Date Apr. 13, 1998 PCT Filed Jul. 9, 1996 PCT Pub. No. WO98/02013 PCT Pub. Date Jan. 15, 1998The invention relates to a switching device which transports data packets from input ports to selected output ports. The payload of the packets is stored in a storage means. A switching means is arranged which has more switch outputs than switch inputs and which switches sequentially between one switch input and several switch outputs while storing the payloads. Furthermore, the invention relates to a storing method which uses switching means to store payloads in a sequential order and to a switching apparatus comprising several switching devices. Furthermore, the invention relates to systems using the switching device as a scaleable module.
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公开(公告)号：DE60042493D1
公开(公告)日：2009-08-13
申请号：DE60042493
申请日：2000-11-21
Applicant: IBM
Inventor： AYDEMIR METIN , BASS BRIAN MITCHELL , JEFFRIES CLARK DEBS , ROVNER SONIA KIANG , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , GORTI BRAHMANAND KUMAR , HEDDES MARCO
IPC: H04L47/30
Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.
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公开(公告)号：AT431028T
公开(公告)日：2009-05-15
申请号：AT00959159
申请日：2000-08-24
Applicant: IBM
Inventor： ALLEN JAMES , BASS BRIAN , CALVIGNAC JEAN , GAUR SANTOSH , HEDDES MARCO , SIEGEL MICHAEL , VERPLANKEN FABRICE
Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
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公开(公告)号：CA2387101C
公开(公告)日：2006-01-03
申请号：CA2387101
申请日：2000-11-21
Applicant: IBM
Inventor： GALLO ANTHONY MATTEO , ROVNER SONIA KIANG , SIEGEL MICHAEL STEVEN , JEFFRIES CLARK DEBS , HEDDES MARCO , GORTI BRAHMANAND KUMAR , BASS BRIAN MITCHELL , AYDEMIR METIN
IPC: H04L47/30
Abstract: Methods, apparatus and program products for controlling a flow of a pluralit y of packets in a computer network are disclosed. The computer network include s a device defining a queue. The methods, apparatus and program products inclu de determining a queue level for the queue and determining an offered rate of t he plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, base d on the queue level, the offered rate and a previous value of the transmissio n fraction so that the transmission fraction and the queue level are criticall y damped if the queue level is between at least a first queue level and a seco nd queue level. Several embodiments are disclosed in which various techniques a re used to determine the manner of the control.
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公开(公告)号：DE60203380D1
公开(公告)日：2005-04-28
申请号：DE60203380
申请日：2002-01-28
Applicant: IBM
Inventor： BASSO CLAUDE , CALVIGNAC LOUIS , HEDDES MARCO , LOGAN FRANKLIN , VERPLANKEN JEAN
Abstract: Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.
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Patent Agency Ranking
公开(公告)号：AT291802T
公开(公告)日：2005-04-15
申请号：AT02715591
申请日：2002-01-28
Applicant: IBM
Inventor： BASSO CLAUDE , CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
Abstract: Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.
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公开(公告)号：AT280411T
公开(公告)日：2004-11-15
申请号：AT00983409
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：CZ20032126A3
公开(公告)日：2004-01-14
申请号：CZ20032126
申请日：2002-02-20
Applicant: IBM
Inventor： VERPLANKEN FABRICE JEAN , CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN
IPC: H04L12/861 , H04L12/00
Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
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公开(公告)号：AU2016601A
公开(公告)日：2001-07-16
申请号：AU2016601
申请日：2000-12-21
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：DE69129851T2
公开(公告)日：1999-03-25
申请号：DE69129851
申请日：1991-09-13
Applicant: IBM
Inventor： HEDDES MARCO , LUIJTEN RONALD PETER
Abstract: The present invention relates to a data transmission system and concerns a method for transforming user frames into fixed length cells, e.g. ATM (Asynchronous Transfer Mode), such that the fixed length cells can be transported through a cell handling switch fabric (11). A hardware implementation of this method consists of two parts, a transmitter (12.1) and a receiver (13.1), both being part of a switching subsystem (10) comprising a switch fabric (11). The transmitter (12.1) buffers user data and segments them into fixed length cells to be transported through said switch (11). The receiver part (13.1) reassembles user data on reception of these cells.
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