公开(公告)号：BR8803628A

公开(公告)日：1989-02-14

申请号：BR8803628

申请日：1988-07-20

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  G11C11/34 ,  G11C11/21

Abstract: A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate (10) and an epitaxial layer (10) thereon including a vertical transistor (14) disposed in a shallow trench (100) stacked above and self-aligned with a capacitor in a deep trench (16). The stacked vertical transistor (4) has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor (14) is a lightly-doped drain structure (21) connected to a bitline element (22). The source (24) of the transistor, located at the bottom of the transistor trench (100) and on top of the center of the trench capacitor (16), is self-aligned and connected to polysilicon (28) contained inside the trench capacitor. Three sidewalls of the access transistor (14) are surrounded by thick oxide isolation (50) and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well (26) and uses the n-well and heavily-doped substrate (10) as the capacitor counter-electrode plate. The cell storage node is the polysilicon (28) inside the trench capacitor. The fabrication method includes steps for growing epitaxial layers wherein an opening (100) is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.

公开(公告)号：DE69126292D1

公开(公告)日：1997-07-03

申请号：DE69126292

申请日：1991-10-28

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI ,  TAIRA YOICHI

IPC: G11C11/407 ,  G11C11/408 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H03K5/02 ,  G11C8/00

Abstract: A wordline driver circuit is shown for a DRAM, the circuit comprising a PMOS transistor structure (58) having one contact coupled to a wordline (60), a second contact coupled to a negative voltage supply and a gate coupled to a control input, the transistor having an N-well (64) about the gate, first and second contacts. An isolating structure (66) is positioned about the N-well (64) to enable it to be a separately controlled from surrounding N-well structures (64). Pulse circuits (52) are coupled to the transistor (58) for applying, when activated, a potential that enables the wordline (60) to transition to a more negative potential. A bias circuit is also provided for biasing the N-well (64) at a first potential and a second lower potential, the second lower potential applied when the pulse circuits (52) are activated. As a result, body effects in the PMOS transistor (58) are minimized while at the same time enabling a boost potential to be applied to the wordline (60).

公开(公告)号：DE69011736D1

公开(公告)日：1994-09-29

申请号：DE69011736

申请日：1990-04-06

Applicant: IBM

Inventor： DHONG SANG H ,  HWANG WEI ,  LU NICKY C C

IPC: H01L21/223 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/108 ,  H01L27/112 ,  H01L29/78 ,  H01L29/784 ,  H01L21/82

Abstract: A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region (15) in a wafer including an epitaxial layer (12) on a substrate (10). A first, heavily doped drain region and bit line element (18) is formed around the trench on the surface of the well (15) , and a second, lightly-doped drain region (24) is formed proximate to the first drain region (18) and self-aligned to the trench sidewalls. A source region (26) is located beneath the trench, which is filled with polysilicon (32), above which is gate and further polysilicon forming a transfer wordline (33). The gate polysilicon (32) is separated from the trench side walls by a layer (30) of gate oxide insulation. The well region (15) at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.

公开(公告)号：DE69100789T2

公开(公告)日：1994-06-23

申请号：DE69100789

申请日：1991-06-11

Applicant: IBM

Inventor： DHONG SANG H ,  HWANG WEI

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

公开(公告)号：DE3786434T2

公开(公告)日：1994-01-20

申请号：DE3786434

申请日：1987-09-08

Applicant: IBM

Inventor： CHIN DAEJE ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00

Abstract: A memory device, in particular, a dynamic random access memory (DRAM), is comprised of a first (12) and a second (14) input/output (I/O) bus, a first (20) and a second (28) I/O sense amplifier, and a first (24) and a second (30) I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal (32) for enabling the operation of the I/O busses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per Column Address Strobe (CAS) cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O busses are alternately enabled, one being enabled when CAS (40) is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.

公开(公告)号：DE3786434D1

公开(公告)日：1993-08-12

申请号：DE3786434

申请日：1987-09-08

Applicant: IBM

Inventor： CHIN DAEJE ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00

Abstract: A memory device, in particular, a dynamic random access memory (DRAM), is comprised of a first (12) and a second (14) input/output (I/O) bus, a first (20) and a second (28) I/O sense amplifier, and a first (24) and a second (30) I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal (32) for enabling the operation of the I/O busses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per Column Address Strobe (CAS) cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O busses are alternately enabled, one being enabled when CAS (40) is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.

公开(公告)号：CA2006745C

公开(公告)日：1993-06-15

申请号：CA2006745

申请日：1989-12-27

Applicant: IBM

Inventor： DHONG SANG H ,  HWANG WEI ,  LU NICKY C-C

IPC: H01L21/223 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/108 ,  H01L27/112 ,  H01L29/78 ,  H01L29/76 ,  H01L29/784

Abstract: A CROSS-POINT LIGHTLY-DOPED DRAIN-SOURCE TRENCH TRANSISTOR AND FABRICATION PROCESS THEREFOR A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region in a wafer including an epitaxial layer on a substrate. A first, heavily doped drain region and bit line element is formed around the trench on the surface of the well, and a second, lightly-doped drain region is formed proximate to the first drain region and self-aligned to the trench sidewalls. A source region is located beneath the trench, which is filled with polysilicon, above which is gate and further polysilicon forming a transfer wordline. The well region at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.

公开(公告)号：DE3880750D1

公开(公告)日：1993-06-09

申请号：DE3880750

申请日：1988-05-20

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY C

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L21/82

Abstract: A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate (16) and an epitaxial layer (36) disposed thereon. A relatively deep polysilicon filled trench (26) is disposed in the epitaxial layer and substrate structure, the deep trench (26) having a composite oxide/nitride insulation layer (24) over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer (36) over the deep trench (26) region, the shallow trench having an oxide insulation layer (46) on its vertical and horizontal surfaces thereof. A neck structure (34) of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench (26) to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer (36) on either side of the shallow trench to form semiconductor device drain (40) junctions and polysilicon material (48) is disposed in the shallow trench and over the epitaxial layer (36) to form semiconductor device transfer gate and wordline regions respectively.

公开(公告)号：AU625691B2

公开(公告)日：1992-07-16

申请号：AU5216990

申请日：1990-03-26

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02 ,  G11C5/14

Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：CA2006745A1

公开(公告)日：1990-11-22

申请号：CA2006745

申请日：1989-12-27

Applicant: IBM

Inventor： DHONG SANG H ,  HWANG WEI ,  LU NICKY C-C

IPC: H01L21/223 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/108 ,  H01L27/112 ,  H01L29/78

Abstract: A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region (15) in a wafer including an epitaxial layer (12) on a substrate (10). A first, heavily doped drain region and bit line element (18) is formed around the trench on the surface of the well (15) , and a second, lightly-doped drain region (24) is formed proximate to the first drain region (18) and self-aligned to the trench sidewalls. A source region (26) is located beneath the trench, which is filled with polysilicon (32), above which is gate and further polysilicon forming a transfer wordline (33). The gate polysilicon (32) is separated from the trench side walls by a layer (30) of gate oxide insulation. The well region (15) at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.