公开(公告)号：SG70046A1

公开(公告)日：2000-01-25

申请号：SG1997004075

申请日：1993-02-01

Applicant: IBM

Inventor： JOSHI RAJIV V ,  CUOMO JEROME J ,  DALAL HORMAZDYAR M ,  HSU LOUIS L

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L21/60 ,  H01L29/43 ,  H01L29/440 ,  H01L29/460 ,  H01L21/44 ,  H01L21/48 ,  H01L29/40

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：DE68917494T2

公开(公告)日：1995-03-30

申请号：DE68917494

申请日：1989-02-03

Applicant: IBM

Inventor： JOSHI RAJIV V

IPC: C23C16/04 ,  C23C16/14 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L29/43 ,  H01L29/78 ,  H01L29/76

公开(公告)号：CA2105039A1

公开(公告)日：1994-05-07

申请号：CA2105039

申请日：1993-08-27

Applicant: IBM

Inventor： BUTI TAQI N ,  HSU LOUIS L ,  JOSHI RAJIV V ,  SHEPARD JOSEPH F

IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L21/441 ,  H01L21/44 ,  H01L21/48

Abstract: A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

公开(公告)号：DE69333604D1

公开(公告)日：2004-09-30

申请号：DE69333604

申请日：1993-02-01

Applicant: IBM

Inventor： JOSHI RAJIV V ,  CUOMO JEROME J ,  DALAL HORMAZDYAR M ,  HSU LOUIS L

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L21/60

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：DE69332917D1

公开(公告)日：2003-05-28

申请号：DE69332917

申请日：1993-02-01

Applicant: IBM

Inventor： JOSHI RAJIV V ,  CUOMO JEROME J ,  DALAL HORMAZDYAR M ,  HSU LOUIS L

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  C23C14/04

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：SG70044A1

公开(公告)日：2000-01-25

申请号：SG1997004071

申请日：1993-02-01

Applicant: IBM

Inventor： JOSHI RAJIV V ,  CUOMO JEROME J ,  DALAL HORMAZDYAR M ,  HSU LOUIS L

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L21/60 ,  H01L29/43 ,  H01L29/440 ,  H01L29/460 ,  H01L21/44 ,  H01L21/48 ,  H01L29/40

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：SG70043A1

公开(公告)日：2000-01-25

申请号：SG1997004069

申请日：1993-02-01

Applicant: IBM

Inventor： JOSHI RAJIV V ,  CUOMO JEROME J ,  HSU LOUIS L ,  DALAL HORMAZDYAR M

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L21/60 ,  H01L29/43 ,  H01L29/440 ,  H01L29/460 ,  H01L21/44 ,  H01L21/48 ,  H01L29/40

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：DE69307274D1

公开(公告)日：1997-02-20

申请号：DE69307274

申请日：1993-10-05

Applicant: IBM

Inventor： BUTI TAQI N ,  JOSHI RAJIV V ,  SHEPARD JOSEPH F ,  HSU LOUIS LU-CHEN

IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L23/535

Abstract: A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

公开(公告)号：DE3868967D1

公开(公告)日：1992-04-16

申请号：DE3868967

申请日：1988-03-25

Applicant: IBM

Inventor： JOSHI RAJIV V

IPC: H01L21/285 ,  C23C16/02 ,  C23C16/14 ,  C23C16/24 ,  C23C16/44 ,  C23C16/50 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/31

Abstract: A method is described for depositing thick, low-stress refractory metal films on a substrate. For example, a layer of tungsten of any required thickness may be deposited by the silicon reduction of tungsten hexafluoride in a CVD reactor. This is accomplished by alternating the process step of plasma depositing an amorphous silicon film, with the process step of exposing the silicon film to tungsten hexafluoride until the required thickness of tungsten is reached. The thickness of the deposited amorphous silicon film must be less than the thickness at which the conversion of silicon to tungsten becomes self-limiting to assure that all of the amorphous silicon is converted. The bombardment of the silicon during the plasma deposition "hammers" the underlying tungsten film and relieves the stress in the film.

公开(公告)号：CA1273439A

公开(公告)日：1990-08-28

申请号：CA565452

申请日：1988-04-29

Applicant: IBM

Inventor： BRODSKY STEPHEN B ,  MOY DAN ,  JOSHI RAJIV V

IPC: H01L23/52 ,  H01L21/3205 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

Abstract: YO986-082 A gate structure for integrated circuit devices which includes a work function layer, a low resistivity layer, and an electrically conductive barrier layer between the two other layers to prevent the other two layers from intermixing. The work function controlling layer is preferably selected from the group of tungsten, molybdenum, their silicides, or a combination thereof.