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    High performance PCI with backward compatibility
    21.
    发明专利
    High performance PCI with backward compatibility 未知

    公开(公告)号：IE990422A1

    公开(公告)日：2000-03-22

    申请号：IE990422

    申请日：1999-05-25

    Applicant: IBM

    Inventor： NEAL DANNY MARVIN ,  THURBER STEVEN MARK ,  BEUKEMA BRUCE LEROY ,  FUHS RONALD EDWARD ,  KELLEY RICHARD ALLEN

    IPC: G06F13/40 ,  G06F13/368

    Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.

    A method and apparatus for adding and removing components of a data processing system without powering down
    23.
    发明专利
    A method and apparatus for adding and removing components of a data processing system without powering down 未知

    公开(公告)号：GB2334120A

    公开(公告)日：1999-08-11

    申请号：GB9909356

    申请日：1997-09-30

    Applicant: IBM

    Inventor： GUTHRIE GUY LYNN ,  NEAL DANNY MARVIN ,  KELLEY RICHARD ALLEN

    IPC: G06F13/40 ,  G06F1/00

    Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter (202a), residing within a Host Bridge (202), Control and Power Logic (208), and a plurality of in-line switch modules (326, 328) coupled to a bus. Each of the in-line switch modules (326, 328) provides isolation for load(s) connected thereto. The Host Bridge (202) in combination with the Control and Power Logic (208) implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).

    ENHANCED HIGH PERFORMANCE PCI
    24.
    发明专利
    ENHANCED HIGH PERFORMANCE PCI 未知

    公开(公告)号：CA2236060A1

    公开(公告)日：1998-12-11

    申请号：CA2236060

    申请日：1998-04-28

    Applicant: IBM

    Inventor： NEAL DANNY MARVIN ,  THURBER STEVEN MARK ,  CLOUSER PAUL L ,  JOHNS CHARLES RAY ,  KELLEY RICHARD ALLEN

    IPC: G06F13/00 ,  G06F13/368 ,  G06F13/38

    Abstract: A peripheral component interconnect (PCI) bus is adapted for differential signal ling. Two signal lines are providing for each bus signal and information is encoded as either a polarity or a magnitude of a voltage difference between the two signal lines. En hanced PCI compliant devices include drivers and receivers capable of differential sign alling. The resulting bus architecture supports clocking data on both edges as well as sourc e synchronous clocking. The enhanced PCI bus architecture also supports data block ing, pacing, split transactions, and synchronization commands.

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