公开(公告)号：DE3789416T2

公开(公告)日：1994-10-27

申请号：DE3789416

申请日：1987-10-16

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/04 ,  H01L21/285 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

Abstract: A one-device shared trench memory cell, in which the polysilicon (22,24) and dielectric layers (26,26A) within the trench (20) extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder (36). The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide a bridge contact (30) that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode (34) to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.

公开(公告)号：DE3788499T2

公开(公告)日：1994-06-30

申请号：DE3788499

申请日：1987-08-18

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94

Abstract: A semiconductor trench capacitor structure (240) having a self-aligned isolation structure formed within the trench. The trench isolation structure consists of a thick isolating layer (340, 360) formed along the upper portion of the trench side walls. The trench isolation structure facilitates the construction of trench capacitors of greater storage capacity in a given space and allows the capacitors to abut adjacent capacitors and other devices.

公开(公告)号：DE3788499D1

公开(公告)日：1994-01-27

申请号：DE3788499

申请日：1987-08-18

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94

Abstract: A semiconductor trench capacitor structure (240) having a self-aligned isolation structure formed within the trench. The trench isolation structure consists of a thick isolating layer (340, 360) formed along the upper portion of the trench side walls. The trench isolation structure facilitates the construction of trench capacitors of greater storage capacity in a given space and allows the capacitors to abut adjacent capacitors and other devices.

公开(公告)号：DE3072095D1

公开(公告)日：1988-06-30

申请号：DE3072095

申请日：1980-11-20

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  KENNEY DONALD MCALPINE

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/336

Abstract: A method for providing self-aligned conductors in vertically integrated semiconductor devices which includes providing recesses in the surface of a semiconductor substrate for the fabrication of V-groove devices, providing a conductive layer over the surface and then applying a layer of masking material over the conductive layer to form a planar upper surface, selectively etching the masking material until it remains only in the recesses and then selectively etching the exposed portion of the conductive layer.

公开(公告)号：DE3371264D1

公开(公告)日：1987-06-04

申请号：DE3371264

申请日：1983-10-11

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  GEIPEL HENRY JOHN ,  KENNEY DONALD MCALPINE

IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

公开(公告)号：DE3463332D1

公开(公告)日：1987-05-27

申请号：DE3463332

申请日：1984-05-28

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE ,  MANDELMAN JACK ALLAN

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/772 ,  H03K17/041 ,  H03K17/687 ,  H03K19/017 ,  H03K17/04

Abstract: A driver circuit is provided which includes a field effect transistor having first and second spaced apart semiconductor regions of a given conductivity type and a third semiconductor region of a conductivity type opposite to the given conductivity type interposed between the first and second regions and having a given sustaining voltage serially connected with a capacitor. The circuit further includes means for applying between the first and second spaced apart regions a given supply voltage having a magnitude greater than the magnitude of the sustaining voltage and less than the breakdown voltage of a PN junction formed in the transistor and means including a control voltage applied to the gate electrode of the transistor for initiating current flow between the first and second spaced apart regions when the given supply voltage is applied between the first and second spaced apart regions.

公开(公告)号：AT26897T

公开(公告)日：1987-05-15

申请号：AT83110131

申请日：1983-10-11

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  GEIPEL HENRY JOHN JR ,  KENNEY DONALD MCALPINE

IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

公开(公告)号：DE3165658D1

公开(公告)日：1984-09-27

申请号：DE3165658

申请日：1981-05-25

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  KENNEY DONALD MCALPINE ,  THOMA NANDOR GYORGY

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78 ,  H01L29/60 ,  H01L21/90

Abstract: High density VMOSFET devices, particularly single transistor memory cells, are provided by use of a series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode subsequently acts as a self-aligned mask to define implanted source/drain regions also within the V-groove and to enable second level interconnecting metallurgy contacts to be formed along the sidewalls of the V-groove.