公开(公告)号：DE112012000965T8

公开(公告)日：2014-06-05

申请号：DE112012000965

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH ,  BROWN MARY DOUGLASS

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00

公开(公告)号：MY117126A

公开(公告)日：2004-05-31

申请号：MYPI9801505

申请日：1998-04-03

Applicant: IBM

Inventor： CHEONG HOICHI ,  JORDAN PAUL JOSEPH ,  LE HUNG QUI

IPC: G06F9/06 ,  G06F9/22 ,  G06F9/38

Abstract: A DATA PROCESSING SYSTEM (100) INDICATES THAT AN INSTRUCTION DOES NOT HAVE AVAILABLE DATA BECAUSE OF A CACHE MISS OR BECAUSE OF A NON-CACHE-MISS DELAY. WHEN THE INSTRUCTION IS NOT ABLE TO ACCESS THE AVAILABLE DATA AND A CACHE MISS RESULTS, INSTRUCTIONS WHICH ARE DEPENDENT ON THE ISSUED INSTRUCTION ARE NOT ISSUED. HOWEVER, IF THE LOAD EXECUTION IS DELAYED BECAUSE OF A NON-CACHE-MISS DELAY, THEN THE INSTRUCTIONS WHICH ARE DEPENDENT ON THE ISSUED INSTRUCTION ARE ALSO ISSUED IN ANTICIPATION OF A SUCCESSFUL LOAD INSTRUCTION EXECUTION IN A NEXTTIMING CYCLE. THROUGH THE USE OF THIS ISSUING MECHANISM, THE EFFICIENCY OF THE DATA PROCESSING SYSTEM IS INCREASED AS AN EXECUTION UNIT IS BETTER ABLE TO UTILIZE ITS PIPELINE. (FIG. 2)

公开(公告)号：FR2800482B1

公开(公告)日：2003-06-13

申请号：FR0011605

申请日：2000-09-12

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  LE HUNG QUI ,  MOORE CHARLES ROBERTS

IPC: G06F9/38 ,  G06F15/04

Abstract: A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.

公开(公告)号：FR2800482A1

公开(公告)日：2001-05-04

申请号：FR0011605

申请日：2000-09-12

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  LE HUNG QUI ,  MOORE CHARLES ROBERTS

IPC: G06F9/38 ,  G06F15/04

Abstract: The instruction handling reads a set of instructions and organizes them into a group of instructions in which each instruction shares a common group label, indicating its order in relation to other instruction groups. An entry in an execution table is attributed to the instruction group to track execution state, with the group label recorded in the instruction table as instructions are executed.

公开(公告)号：MX9802611A

公开(公告)日：1998-11-29

申请号：MX9802611

申请日：1998-04-03

Applicant: IBM

Inventor： CHEONG HOICHI ,  JORDAN PAUL JOSEPH ,  LE HUNG QUI

IPC: G06F9/38 ,  G11B03/00

Abstract: Durante la operacion de un sistema procesador de datos canalizado, una tabla de instrucciones interrumpibles se usa para almacenar identificadores de objetivos asociados con instrucciones las cuales pueden resultar en una ejecucion especulativa. Durante la operacion de la tabla de instrucciones interrumpible, un indicador, mencionado como un indicador de entrada de memoria temporal de terminacion de instrucciones, señala a un fondo de la tabla de instrucciones interrumpible si esa tabla incluye alguna instruccion. Una entrada en el fondo de la tabla de instrucciones interrumpible es una siguiente instruccion por completar. Esta entrada incluye un identificador de objetivo, nombrado como la TID no especulativa y no interrumpible, se puede usar para liberar fuentes mantenidas para todas las instrucciones ejecutadas anteriormente. El sistema procesador de datos determina el valor de la TID no especulativa y no interrumpible, para asegurar que se conserve una determinacion de orden y suministre un punto de ejecucion especulativa verdadera.