公开(公告)号：HK90993A

公开(公告)日：1993-09-10

申请号：HK90993

申请日：1993-09-02

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/82

Abstract: Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

公开(公告)号：DE3583004D1

公开(公告)日：1991-07-04

申请号：DE3583004

申请日：1985-11-05

Applicant: IBM

Inventor： CHAO HU HERBERT ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/00

Abstract: @ A voltage boosting circuit combination for semiconductor memory word-lines having a charge/discharge circuit including a first pair of MOSFET's (20, 24) and connected to a first clock signal ΦA. An output lead (12) is connected from the charge/discharge circuit to a word-line of a semiconductor memory. The first clock signal ΦA thereon is connected to the charge/discharge circuit for actuating the MOSFET's to produce a voltage change on the output lead from a first voltage level to a second voltage level. The circuit combination also includes a threshold voltage circuit having a second pair of MOSFET's (34), which is connected to a second clock signal ΦC for controlling the voltage level in the threshold voltage circuit. A lead (19) is provided connecting the threshold voltage circuit to the charge/discharge circuit. The circuit combination further includes an output signal boosting circuit having a third pair of MOSFET's (30, 32) which is connected to a third clock signal OD for actuating the MOSFET's to produce a voltage boosting signal. A capacitor device (28) is provided for connecting the boosting circuit to the output lead (12) for applying the voltage boosting signal from the voltage boosting circuit to the output lead for enhancing the voltage level change on the output lead to the first voltage level from the second voltage level.

公开(公告)号：AU609167B2

公开(公告)日：1991-04-26

申请号：AU2033688

申请日：1988-08-02

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L21/82 ,  H01L29/94

Abstract: A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate (10) and an epitaxial layer (10) thereon including a vertical transistor (14) disposed in a shallow trench (100) stacked above and self-aligned with a capacitor in a deep trench (16). The stacked vertical transistor (4) has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor (14) is a lightly-doped drain structure (21) connected to a bitline element (22). The source (24) of the transistor, located at the bottom of the transistor trench (100) and on top of the center of the trench capacitor (16), is self-aligned and connected to polysilicon (28) contained inside the trench capacitor. Three sidewalls of the access transistor (14) are surrounded by thick oxide isolation (50) and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well (26) and uses the n-well and heavily-doped substrate (10) as the capacitor counter-electrode plate. The cell storage node is the polysilicon (28) inside the trench capacitor. The fabrication method includes steps for growing epitaxial layers wherein an opening (100) is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.

公开(公告)号：DE3675423D1

公开(公告)日：1990-12-13

申请号：DE3675423

申请日：1986-04-08

Applicant: IBM

Inventor： CHAO HU HERBERT ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C8/00 ,  G11C11/401

Abstract: A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters are used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock.A high performance decoder circuit is provided in combination with the aforesaid SMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.In order to boost the word-line below 0 V, a negative substrate bias is provided which avoids the junction forward-biasing due to voltage undershoot below 0 V at NMOS source or drain, thus simplifying the design and speeding up the word-line clock pull-down when compared to the word-line boost clock circuit without using the substrate bias.An embodiment is shown in the drawings in which block 11 is a NOR gate which sums the two clock signals ø B and ø AS . Blocks 13 and 15 include a chain of delay circuits. Block 17 is a delay circuit for clock signal ø B . Blocks 19 and 21 also include chains of delay circuits. Block 23 functions as a gate wherein clock signal ø C is stored at a device Q 24 and is gated to delay block 19 when a signal is applied to device Q23.Block 25 is a NOR circuit for delayed signal ø c from block 15 and delayed signal ø D from block 21. Block 27 is a NAND circuit for the output of NOR circuit 25 and an external boost output signal (from block 33). Block 29 is an internal boost circuit for node 22 to control the device Q,. Block 31 is a clock driver means and block 22 is an external boosting means. Block 35 performs a NAND function for the delayed ø D signal from block 21 and the delayed ø B signal from block 17.

公开(公告)号：DE3786434T2

公开(公告)日：1994-01-20

申请号：DE3786434

申请日：1987-09-08

Applicant: IBM

Inventor： CHIN DAEJE ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00

Abstract: A memory device, in particular, a dynamic random access memory (DRAM), is comprised of a first (12) and a second (14) input/output (I/O) bus, a first (20) and a second (28) I/O sense amplifier, and a first (24) and a second (30) I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal (32) for enabling the operation of the I/O busses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per Column Address Strobe (CAS) cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O busses are alternately enabled, one being enabled when CAS (40) is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.

公开(公告)号：DE3786434D1

公开(公告)日：1993-08-12

申请号：DE3786434

申请日：1987-09-08

Applicant: IBM

Inventor： CHIN DAEJE ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00

Abstract: A memory device, in particular, a dynamic random access memory (DRAM), is comprised of a first (12) and a second (14) input/output (I/O) bus, a first (20) and a second (28) I/O sense amplifier, and a first (24) and a second (30) I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal (32) for enabling the operation of the I/O busses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per Column Address Strobe (CAS) cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O busses are alternately enabled, one being enabled when CAS (40) is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.

公开(公告)号：AU625691B2

公开(公告)日：1992-07-16

申请号：AU5216990

申请日：1990-03-26

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02 ,  G11C5/14

Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：DE3777514D1

公开(公告)日：1992-04-23

申请号：DE3777514

申请日：1987-05-05

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN ,  MACHESNEY BRIAN JOHN

IPC: H01L27/04 ,  G11C11/24 ,  H01L21/20 ,  H01L21/205 ,  H01L21/74 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands (18) which forms a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor (80, 84, 98) formed in monocrystalline silicon (30) stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window (52) for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.

公开(公告)号：AT73962T

公开(公告)日：1992-04-15

申请号：AT87106472

申请日：1987-05-05

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN ,  MACHESNEY BRIAN JOHN

IPC: H01L27/04 ,  G11C11/24 ,  H01L21/20 ,  H01L21/205 ,  H01L21/74 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands (18) which forms a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor (80, 84, 98) formed in monocrystalline silicon (30) stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window (52) for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.

公开(公告)号：AU5216990A

公开(公告)日：1990-11-01

申请号：AU5216990

申请日：1990-03-26

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02 ,  G11C5/14

Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.