公开(公告)号：JP2007227921A

公开(公告)日：2007-09-06

申请号：JP2007037720

申请日：2007-02-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN ,  YANG CHIH-CHAO

IPC: H01L21/3205 ,  H01L21/312 ,  H01L21/316

CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31633 ,  H01L21/7682 ,  H01L21/76831

Abstract: PROBLEM TO BE SOLVED: To provide a dielectric having a reduced dielectric constant, and to provide its manufacturing method.
SOLUTION: In a first embodiment, a first method of manufacturing a dielectric having a reduced dielectric constant is provided. The first method includes the steps of: (1) forming a dielectric layer including a trench on a substrate; and (2) forming a cladding region in the dielectric layer by forming a plurality of air gaps in the dielectric layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric. Numerous other aspects are provided.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有降低的介电常数的电介质，并提供其制造方法。 解决方案：在第一实施例中，提供了制造具有降低的介电常数的电介质的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成包括沟槽的电介质层; 以及（2）通过沿着沟槽的侧壁和底部中的至少一个在电介质层中形成多个空气间隙来形成电介质层中的包层区域，以便降低电介质的有效介电常数。 提供了许多其他方面。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007227920A

公开(公告)日：2007-09-06

申请号：JP2007037510

申请日：2007-02-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  TONTI WILLIAM R ,  HORAK DAVID VACLAV ,  ETHAN HARRISON CANNON ,  FURUKAWA TOSHIHARU ,  CHARLES WILLIAM KOBURGER III ,  JIMMY KONSTANTINOS KONTOS ,  HAKEY MARK C

IPC: H01L27/08 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor and a device structure which suppress the latch-up in a bulk CMOS device.
SOLUTION: The method includes a step of forming a trench in a semiconductor material of a substrate, while the trench has a first side wall disposed between a pair of doped wells demarcated in the semiconductor material of the substrate. The method further includes a step of forming an etching mask in the trench to mask partially the basal surface of the trench, and successively a step of removing the semiconductor material of the substrate exposing in the basal surface which has been partially masked and demarcating a second side wall which deepens the trench and has been narrowed. A dielectric material is filled in the deepened trench to demarcate trench separation regions of devices constructed in the doped wells. The dielectric material filled in the extended part of the deepened trench improves the suppression of the latch-up.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造半导体的方法和抑制体CMOS器件中的闩锁的器件结构。 解决方案：该方法包括在衬底的半导体材料中形成沟槽的步骤，而沟槽具有设置在衬底的半导体材料中划分的一对掺杂阱之间的第一侧壁。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩模沟槽的基面的步骤，并且连续地去除已经被部分掩蔽并且划分第二个的基底表面中露出的衬底的半导体材料的步骤 侧壁加深了沟槽并缩小了。 将介电材料填充在加深的沟槽中以划定在掺杂阱中构造的器件的沟槽分离区域。 填充在加深沟槽的延伸部分中的电介质材料改善了闩锁的抑制。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007201463A

公开(公告)日：2007-08-09

申请号：JP2007009439

申请日：2007-01-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHARLES WILLIAM KOBURGER III ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK ALLAN

IPC: H01L27/08 ,  H01L21/265 ,  H01L21/76 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/76237 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/1087 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device adapted to reduce latchups. SOLUTION: The semiconductor device includes (1) a shallow-trench-isolation (STI) oxide region; (2) a first metal-oxide-semiconductor field-effect transistor (MOSFET) coupled to a first side of the STI oxide region; (3) a second MOSFET coupled to a second side of the STI oxide region, wherein the portions of the first and second MOSFETs are coupled into a loop to form first and second bipolar junction transistors (BJTs); and (4) a dopant-implanted region, formed below the STI oxide region, where the dopant-implanted region forms a portion of the BJT loop and is adapted to reduce a gain of the loop. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供适于减少闭锁的半导体器件。 解决方案：半导体器件包括（1）浅沟槽隔离（STI）氧化物区域; （2）耦合到所述STI氧化物区域的第一侧的第一金属氧化物半导体场效应晶体管（MOSFET）; （3）耦合到所述STI氧化物区域的第二侧的第二MOSFET，其中所述第一和第二MOSFET的所述部分耦合到环中以形成第一和第二双极结型晶体管（BJT）; 和（4）掺杂剂注入区域，其形成在STI氧化物区域下方，其中掺杂剂注入区域形成BJT环路的一部分并且适于减小环路的增益。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004056119A

公开(公告)日：2004-02-19

申请号：JP2003160554

申请日：2003-06-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  MANDELMAN JACK ALLAN ,  TONTI WILLIAM R

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/76237

Abstract: PROBLEM TO BE SOLVED: To improve a leakage current characteristic at or below the threshold of a trench discrete type FET element.
SOLUTION: A slot in a vertical direction is formed in an stacked structure 14 adhered to a silicon substrate 10 covered with an oxide 12, and thereafter a spacer is formed on the sidewall of the slot. Then, a trench is formed in the substrate 10 by etching. A horizontal ledge appears adjacent to the trench, on the exposed surface of the substrate covered with the oxide by removal of the spacer. The conduction of an end in the element is suppressed by injecting a proper impurity into this ledge.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提高等于或低于沟槽离散型FET元件的阈值的漏电流特性。 解决方案：垂直方向的槽形成在粘附到被氧化物12覆盖的硅衬底10上的堆叠结构14中，然后在槽的侧壁上形成间隔件。 然后，通过蚀刻在衬底10中形成沟槽。 水平凸缘出现在沟槽附近，通过移除间隔件，在被氧化物覆盖的基板的暴露表面上。 通过在该凸缘中注入适当的杂质来抑制元件中端部的导通。 版权所有（C）2004，JPO

公开(公告)号：JP2003303898A

公开(公告)日：2003-10-24

申请号：JP2003078141

申请日：2003-03-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： BERTIN CLAUDE L ,  JOHN JOSEF ELLIS-MONAHAN ,  ERIK RAY HEDBERG ,  HOOK TERENCE B ,  MANDELMAN JACK ALLAN ,  EDWARD JOSEF NOWACK ,  PRICER WILBUR DAVID ,  MIN HO TON ,  TONTI WILLIAM R

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H03K17/06 ,  H03K19/00 ,  H03K19/094 ,  H03K19/0944

CPC classification number: H03K19/0027 ,  H01L29/78606 ,  H03K2217/0018

Abstract: PROBLEM TO BE SOLVED: To provide a switched body SOI CMOS circuit which is provided with an FET element for increasing a FET element threshold voltage.
SOLUTION: A circuit having an SOI element is connected with a body bias voltage, via a switch for selectively connecting a body bias voltage signal with an SOI element body. An NMOS or PMOS SOI element is used as the switched body SOI element. An FET is used as a switch. A gate terminal of the SOI element is connected with an FET element. A gate of the SOI element controls the FET switch connection of the body bias voltage signal to the SOI element, and adjusts a threshold value voltage of the SOI element. A logic circuit including the SOI element and a fabrication process for the SOI element are similarly disclosed.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种开关体SOI CMOS电路，其提供有用于增加FET元件阈值电压的FET元件。 解决方案：具有SOI元件的电路通过用于选择性地将体偏置电压信号与SOI元件体连接的开关与体偏置电压连接。 NMOS或PMOS SOI元件用作开关体SOI元件。 使用FET作为开关。 SOI元件的栅极端子与FET元件连接。 SOI元件的栅极控制体偏置电压信号与SOI元件的FET开关连接，并调整SOI元件的阈值电压。 类似地公开了包括SOI元件的逻辑电路和用于SOI元件的制造工艺。 版权所有（C）2004，JPO

公开(公告)号：JPH10214965A

公开(公告)日：1998-08-11

申请号：JP855498

申请日：1998-01-20

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  GARRY BELLA BRONNER ,  MANDELMAN JACK ALLAN ,  NESBIT LARRY A

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234

Abstract: PROBLEM TO BE SOLVED: To adjust the threshold voltage at the corner of a device without requiring any additional mask by doping the central part of a channel region at some concentration and doping a channel region adjacent to a corner region at a higher concentration. SOLUTION: N type (arsenic) dopant ions 19 are implanted compensatingly. The compensatory implantation is performed in order to compensate for the threshold voltage implantation at the part of the side wall of STI trench structures 18a-18c contiguous to the corner of a substrate 12 other than the corner region 25 and to suppress the effect of P-type ion implantation 21 in the channel region onto the following stage by means of N type doping ions 19 so that the corner region 25 has a higher doping concentration after boron B doping stage. A spacer 16 prevents the compensatory implantation at the corner of the device except the central channel regions 20a, 20b, 20c and 20d.

公开(公告)号：SG70142A1

公开(公告)日：2000-01-25

申请号：SG1998005847

申请日：1998-12-16

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY PETER ,  MANDELMAN JACK ALLAN ,  RADENS CARL J ,  TONTI WILLIAM ROBERT PATRICK

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

Abstract: Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

公开(公告)号：DE3463332D1

公开(公告)日：1987-05-27

申请号：DE3463332

申请日：1984-05-28

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE ,  MANDELMAN JACK ALLAN

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/772 ,  H03K17/041 ,  H03K17/687 ,  H03K19/017 ,  H03K17/04

Abstract: A driver circuit is provided which includes a field effect transistor having first and second spaced apart semiconductor regions of a given conductivity type and a third semiconductor region of a conductivity type opposite to the given conductivity type interposed between the first and second regions and having a given sustaining voltage serially connected with a capacitor. The circuit further includes means for applying between the first and second spaced apart regions a given supply voltage having a magnitude greater than the magnitude of the sustaining voltage and less than the breakdown voltage of a PN junction formed in the transistor and means including a control voltage applied to the gate electrode of the transistor for initiating current flow between the first and second spaced apart regions when the given supply voltage is applied between the first and second spaced apart regions.