公开(公告)号：SG70142A1

公开(公告)日：2000-01-25

申请号：SG1998005847

申请日：1998-12-16

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY PETER ,  MANDELMAN JACK ALLAN ,  RADENS CARL J ,  TONTI WILLIAM ROBERT PATRICK

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

Abstract: Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

公开(公告)号：SG66413A1

公开(公告)日：1999-07-20

申请号：SG1997004090

申请日：1997-11-19

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  HOWELL WAYNE JOHN ,  TONTI WILLIAM ROBERT PATRICK ,  ZALESNSKI JERZY MARIA

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92 ,  H01L21/76

Abstract: An integrated high-performance decoupling capacitor, formed on a semiconductor chip, using the substrate of the chip itself in conjunction with a metallic deposit formed on the presently unused chip back surface and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor in close proximity to the active circuit on the chip requiring such decoupling capacitance. Specifically the present invention achieves this desirable result by providing a dielectric layer on the unused backside of the chip and forming a metal deposit on the formed backside dielectric layer and an electrical connection, between the metallic deposit and the active chip circuit via a through hole in the chip. Very precise decoupling of selected areas in the chip circuit can be achieved by forming precise and multiple metal deposits of either the same size or of varying sizes to define specific capacitances and individually connecting these deposits to the circuit areas needing the precise decoupling capacitance.