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公开(公告)号：CA2413420C
公开(公告)日：2008-09-02
申请号：CA2413420
申请日：2001-06-26
Applicant: IBM
Inventor： BENAYOUN ALAIN , TOUBOL GILLES , MICHEL PATRICK
IPC: G06F13/00 , G06F13/10 , G06F3/01 , G06F3/0354 , G06F3/038
Abstract: A system for establishing wireless connection between a peripheral device and an intelligent device in a multi-computers environment having a plurality of intelligent devices, is disclosed. The system is in part included within the peripheral device which is preferably a mouse device and also is included within the intelligent device which is preferably a computer system. Specific routines of the system allow a user to work with any of the intelligent devices using only the one mouse device.
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公开(公告)号：DE60034009T2
公开(公告)日：2007-11-29
申请号：DE60034009
申请日：2000-09-28
Applicant: IBM
Inventor： BENAYOUN ALAIN , LE PENNEC JEAN FRANCOIS , MICHEL PATRICK
IPC: H04L9/08
Abstract: The invention discloses a method of updating, in nodes on both ends of a secure link, the encryption key they share to encrypt and decrypt data. When having to transmit data from one of the nodes towards its peer remote node, a data base in the forwarding node, is first updated from the data to be transmitted. Then, encryption is performed and data transmitted to the peer remote node while a next-to-use encryption key is derived from the new contents of the data base. When received, data are decrypted with the current value of the encryption key and the peer remote node data base is updated identically from the received decrypted data after which a next-to-use encryption key is derived, thereby obtaining in the peer remote node, a next-to-use identical key. The data base is preferably the dictionary of a data compression/decompression system used simultaneously with encryption/decryption to transmit data over the secure link. While keys are frequently updated, for improved security, the invention does not require that key updates need to be actually distributed.
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公开(公告)号：FR2811180B1
公开(公告)日：2007-08-31
申请号：FR0104882
申请日：2001-04-10
Applicant: IBM
Inventor： LE PENNEC JEAN FRANCOIS , FIESCHI JACQUES , MICHEL PATRICK , BENAYOUN ALAIN
IPC: H04L49/111
Abstract: Data transmission system for transmitting packets of data from a source workstation ( 10 ) to a destination workstation ( 18 ) wherein the packets of data are transmitted over at least an IP network ( 14 ) between an ingress node ( 16 ) connected to the source workstation and an egress node ( 20 ) connected to the destination workstation, wherein each router within the intermediary nodes along the data path from the ingress node to the egress node determines the best route in a routing table defined by the contents of a field contained in each packet of data being received. For this, the router of the ingress node comprises a configuration table which defines the contents of the TOS field in function of information associated with the 4/5 level protocol such as TCP or UDP.
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公开(公告)号：DE60034009D1
公开(公告)日：2007-05-03
申请号：DE60034009
申请日：2000-09-28
Applicant: IBM
Inventor： BENAYOUN ALAIN , LE PENNEC JEAN FRANCOIS , MICHEL PATRICK
IPC: H04L9/08
Abstract: The invention discloses a method of updating, in nodes on both ends of a secure link, the encryption key they share to encrypt and decrypt data. When having to transmit data from one of the nodes towards its peer remote node, a data base in the forwarding node, is first updated from the data to be transmitted. Then, encryption is performed and data transmitted to the peer remote node while a next-to-use encryption key is derived from the new contents of the data base. When received, data are decrypted with the current value of the encryption key and the peer remote node data base is updated identically from the received decrypted data after which a next-to-use encryption key is derived, thereby obtaining in the peer remote node, a next-to-use identical key. The data base is preferably the dictionary of a data compression/decompression system used simultaneously with encryption/decryption to transmit data over the secure link. While keys are frequently updated, for improved security, the invention does not require that key updates need to be actually distributed.
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公开(公告)号：FR2811787B1
公开(公告)日：2003-04-04
申请号：FR0105479
申请日：2001-04-24
Applicant: IBM CORP INTERNAT BUSINESS MAC
Inventor： FIESCHI JACQUES , MICHEL PATRICK , LE PENNEC JEAN FRANCOIS , ROY PASCAL
Abstract: A method for validating an electronic payment by a credit/debit card in a transaction system. The method includes registering a purchase of an article by a buyer using a credit/debit card associated with at least one PIN code, checking that the at least one PIN code is associated with the number of said credit/debit card provided by said buyer to said seller terminal, checking, by said electronic payment center, whether or not said at least one PIN code is valid, and one of: after the at least one PIN code is found to be valid, checking, by said electronic payment center, whether the electronic payment center has received a pre-validation from a third party; after the at least one PIN code is found to be valid, contacting a third party via a communication network and requesting that the third party validate the purchase; and after the at least one PIN code is found to be valid, contacting a third party via a communication network and requesting said at least one PIN code from the third party. The third party is a prime owner of the credit/debit card.
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Patent Agency Ranking
公开(公告)号：FR2805686A1
公开(公告)日：2001-08-31
申请号：FR0014653
申请日：2000-11-14
Applicant: IBM
Inventor： MICHEL PATRICK , OUAZANA CHRISTIAN , SERGENT BERNARD , VERHAEGHE MICHEL
Abstract: The signal transmission reflection removal system has a transmission system (10) having a command circuit and receivers (14-16) with signals transmitted following a multipoint topology. the reflection nulling mechanism has set signals generated of the opposite sign and timing sequences equalising (40) the propagation time together with an algebraic summer which negates the reflection effects.
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公开(公告)号：FR2794259A1
公开(公告)日：2000-12-01
申请号：FR0006085
申请日：2000-05-12
Applicant: IBM
Inventor： BENAYOUN ALAIN , MICHEL PATRICK , LE PENNEC JEAN FRANCOIS , PIN CLAUDE
Abstract: Only one of activation blocks (22-30) associated with the corresponding selected decision block is activated to execute specific micro-instructions. A micro-instructions selection block (46) controls each activation blocks destine for selecting specific micro-instructions among a set of micro-instructions resulting from a content of an operand field of a given instruction.
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公开(公告)号：DE69124743T2
公开(公告)日：1997-08-14
申请号：DE69124743
申请日：1991-11-29
Applicant: IBM
Inventor： BARDET GERARD , LE PENNEC JEAN-FRANCOIS , MICHEL PATRICK , THERIAS PHILIPPE
Abstract: A store and forward mechanism for telecommunication equipments including means (300) for deserializing a HDLC frame of data which is received from a first telecommunication node into a sequence of n-bits words. The frame includes a header, a data field and a frame checking sequence (FCS) generated by said first telecommunication node. The apparatus further includes processing means for generating n-bit words corresponding to a new header of said received HDLC frame. The store and forward apparatus comprises serializing means (600) receiving said processed n-bits words from said storage for generating a new HDLC frame comprising said new header field and a corresponding new FCS which is to be transmitted to said second telecommunication node. The apparatus further includes means (500) receiving the received HDLC frame simultaneously to the deserializing means and which computes a first partial FCS covering the data field only of the HDLC frame, and means (200) for storing that partial FCS. During the forward phase, the n-bits words which are to be transmitted to the next telecommunication node are simultaneously received by the HDLC serializer and by means (800) for computing a second partial FCS covering said data field only. At the end of the serialization process of the data field of the HDLC frame, the two partial results are compared in order to detect the occurence of an error which might have appeared in the storage during the computing of the new header of the frame. The result of that comparison is used as a control signal for altering the value of the FCS computed by the HDLC serializer before it is transmitted to the telecommunication line field of the HDLC frame, the two partial results are compared in order to detect the occurence of an error which might have appeared in the storage during the computing of the new header of the frame. The result of that comparison is used as a control signal for altering the value of the FCS computed by the HDLC serializer before it is transmitted to the telecommunication line. Since the computing of both the first and second partial FCS is respectively performed during the deserializing of the HDLC frame and the serializing of the processed n-bit data words, no extra delay is required. The integrity of data during its storage in RAM is therefore provided without needed additional processing resources since the processor which is included within the store and forward mechanism has its resources which remain fully allocated for the store and forward process.
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公开(公告)号：CA2105353A1
公开(公告)日：1994-06-18
申请号：CA2105353
申请日：1993-09-01
Applicant: IBM
Inventor： AVARGUES DIDIER , CLARA JEAN-LOUIS , LE PENNEC JEAN-FRANCOIS , MICHEL PATRICK , SICSIC PATRICK
IPC: H04M11/00 , G06F15/177 , H04Q11/04 , H04L12/52
Abstract: Method for initializing a set of at least two ISDN adapter cards (210-240) being plugged within a workstation including a main processor and an ISDN primary adapter (222) for allowing the connection of said ISDN adapter cards (210-240) to an ISDN primary gate, each of said ISDN adapter cards being provided with means (640-670) for handling at least one B-channel, first processing means (140) associated with memory storage (140). The ISDN primary adapter (222) comprising second processing means (100) associated with second memory storage. The method involving the step of: performing a polling (12) in said ISDN primary adapter (222) consisting in the transmission of a specific polling pattern to each of said ISDN adapter cards, in response to the reception of said polling pattern in one of said ISDN adapter cards, transmitting a first pattern consisting of a request pattern (14) to said the processor located in the workstation for requiring a loading of the second memory storage with operational code transferred from the workstation to the ISDN adapter card (210) and the ISDN primary adapter (222), in response to the request pattern received by the main processor (260), transmitting a second pattern to the ISDN adapter (222) via the ISDN adapter card (210) that have transmitted the first pattern, so that the main processor in the workstation and the processor in the ISDN primary adapter recognize the ISDN adapter card that has respectively transmitted the first and third pattern to the workstation and to the ISDN primary adapter (222) be considered as the master ISDN adapter card which will be used in the future for the transmission of the control information and the D-channel. Additionally, that ISDN adapter card is used for the downloading of the operational code from the workstation to the memory storage located into the ISDN primary adapter (222). This results in the possibility of loading the different required software routines in the appropriated locations within the cards so that all work together together to handle a full primary ISDN frame.
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公开(公告)号：DE3780640D1
公开(公告)日：1992-08-27
申请号：DE3780640
申请日：1987-10-19
Applicant: IBM
Inventor： CUKIER MAURICE , MARCIANO FREDERIK , MICHEL PATRICK
Abstract: The circuit comprises a delta coder (18) providing a serial bit storing at a rate provided by a clock frequency F in response to digital words provided at a frequency f which is lower than F. An analog integrator (22) provides an output signal (24) representing the digital words. In response to an adjust signal which speeds up or slows down f a circuit modifies, by a set duration, the time of one bit from the delta coder. A corrected pulse is produced in place of the sigma-delta data provided by the corrected when modification of that one bit is detected. The corrected pulse lasts half the set duration and introduces an offset which has the same or opposite polarity of the detected bit when the modified bit is lengthened or shortened respectively.
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